1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __GENWQE_CARD_H__ 8 #define __GENWQE_CARD_H__ 9 #include <linux/types.h> 10 #include <linux/ioctl.h> 11 #define GENWQE_DEVNAME "genwqe" 12 #define GENWQE_TYPE_ALTERA_230 0x00 13 #define GENWQE_TYPE_ALTERA_530 0x01 14 #define GENWQE_TYPE_ALTERA_A4 0x02 15 #define GENWQE_TYPE_ALTERA_A7 0x03 16 #define GENWQE_UID_OFFS(uid) ((uid) << 24) 17 #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0) 18 #define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1) 19 #define GENWQE_APP_OFFS GENWQE_UID_OFFS(2) 20 #define GENWQE_MAX_UNITS 3 21 #define IO_EXTENDED_ERROR_POINTER 0x00000048 22 #define IO_ERROR_INJECT_SELECTOR 0x00000060 23 #define IO_EXTENDED_DIAG_SELECTOR 0x00000070 24 #define IO_EXTENDED_DIAG_READ_MBX 0x00000078 25 #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3)) 26 #define GENWQE_EXTENDED_DIAG_SELECTOR(ring,trace) (((ring) << 8) | (trace)) 27 #define IO_SLU_UNITCFG 0x00000000 28 #define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 29 #define IO_SLU_FIR 0x00000008 30 #define IO_SLU_FIR_CLR 0x00000010 31 #define IO_SLU_FEC 0x00000018 32 #define IO_SLU_ERR_ACT_MASK 0x00000020 33 #define IO_SLU_ERR_ATTN_MASK 0x00000028 34 #define IO_SLU_FIRX1_ACT_MASK 0x00000030 35 #define IO_SLU_FIRX0_ACT_MASK 0x00000038 36 #define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040 37 #define IO_SLU_EXTENDED_ERR_PTR 0x00000048 38 #define IO_SLU_COMMON_CONFIG 0x00000060 39 #define IO_SLU_FLASH_FIR 0x00000108 40 #define IO_SLU_SLC_FIR 0x00000110 41 #define IO_SLU_RIU_TRAP 0x00000280 42 #define IO_SLU_FLASH_FEC 0x00000308 43 #define IO_SLU_SLC_FEC 0x00000310 44 #define IO_SLC_QUEUE_SEGMENT 0x00010000 45 #define IO_SLC_VF_QUEUE_SEGMENT 0x00050000 46 #define IO_SLC_QUEUE_OFFSET 0x00010008 47 #define IO_SLC_VF_QUEUE_OFFSET 0x00050008 48 #define IO_SLC_QUEUE_CONFIG 0x00010010 49 #define IO_SLC_VF_QUEUE_CONFIG 0x00050010 50 #define IO_SLC_APPJOB_TIMEOUT 0x00010018 51 #define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018 52 #define TIMEOUT_250MS 0x0000000f 53 #define HEARTBEAT_DISABLE 0x0000ff00 54 #define IO_SLC_QUEUE_INITSQN 0x00010020 55 #define IO_SLC_VF_QUEUE_INITSQN 0x00050020 56 #define IO_SLC_QUEUE_WRAP 0x00010028 57 #define IO_SLC_VF_QUEUE_WRAP 0x00050028 58 #define IO_SLC_QUEUE_STATUS 0x00010100 59 #define IO_SLC_VF_QUEUE_STATUS 0x00050100 60 #define IO_SLC_QUEUE_WTIME 0x00010030 61 #define IO_SLC_VF_QUEUE_WTIME 0x00050030 62 #define IO_SLC_QUEUE_ERRCNTS 0x00010038 63 #define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038 64 #define IO_SLC_QUEUE_LRW 0x00010040 65 #define IO_SLC_VF_QUEUE_LRW 0x00050040 66 #define IO_SLC_FREE_RUNNING_TIMER 0x00010108 67 #define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108 68 #define IO_PF_SLC_VIRTUAL_REGION 0x00050000 69 #define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000 70 #define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8 * (n)) 71 #define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n) 72 #define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8 * (n)) 73 #define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8 * (n)) 74 #define IO_SLC_CFGREG_GFIR 0x00020000 75 #define GFIR_ERR_TRIGGER 0x0000ffff 76 #define IO_SLC_CFGREG_SOFTRESET 0x00020018 77 #define IO_SLC_MISC_DEBUG 0x00020060 78 #define IO_SLC_MISC_DEBUG_CLR 0x00020068 79 #define IO_SLC_MISC_DEBUG_SET 0x00020070 80 #define IO_SLU_TEMPERATURE_SENSOR 0x00030000 81 #define IO_SLU_TEMPERATURE_CONFIG 0x00030008 82 #define IO_SLU_VOLTAGE_CONTROL 0x00030080 83 #define IO_SLU_VOLTAGE_NOMINAL 0x00000000 84 #define IO_SLU_VOLTAGE_DOWN5 0x00000006 85 #define IO_SLU_VOLTAGE_UP5 0x00000007 86 #define IO_SLU_LEDCONTROL 0x00030100 87 #define IO_SLU_FLASH_DIRECTACCESS 0x00040010 88 #define IO_SLU_FLASH_DIRECTACCESS2 0x00040020 89 #define IO_SLU_FLASH_CMDINTF 0x00040030 90 #define IO_SLU_BITSTREAM 0x00040040 91 #define IO_HSU_ERR_BEHAVIOR 0x01001010 92 #define IO_SLC2_SQB_TRAP 0x00062000 93 #define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008 94 #define IO_SLC2_FLS_MASTER_TRAP 0x00062010 95 #define IO_HSU_UNITCFG 0x01000000 96 #define IO_HSU_FIR 0x01000008 97 #define IO_HSU_FIR_CLR 0x01000010 98 #define IO_HSU_FEC 0x01000018 99 #define IO_HSU_ERR_ACT_MASK 0x01000020 100 #define IO_HSU_ERR_ATTN_MASK 0x01000028 101 #define IO_HSU_FIRX1_ACT_MASK 0x01000030 102 #define IO_HSU_FIRX0_ACT_MASK 0x01000038 103 #define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040 104 #define IO_HSU_EXTENDED_ERR_PTR 0x01000048 105 #define IO_HSU_COMMON_CONFIG 0x01000060 106 #define IO_APP_UNITCFG 0x02000000 107 #define IO_APP_FIR 0x02000008 108 #define IO_APP_FIR_CLR 0x02000010 109 #define IO_APP_FEC 0x02000018 110 #define IO_APP_ERR_ACT_MASK 0x02000020 111 #define IO_APP_ERR_ATTN_MASK 0x02000028 112 #define IO_APP_FIRX1_ACT_MASK 0x02000030 113 #define IO_APP_FIRX0_ACT_MASK 0x02000038 114 #define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040 115 #define IO_APP_EXTENDED_ERR_PTR 0x02000048 116 #define IO_APP_COMMON_CONFIG 0x02000060 117 #define IO_APP_DEBUG_REG_01 0x02010000 118 #define IO_APP_DEBUG_REG_02 0x02010008 119 #define IO_APP_DEBUG_REG_03 0x02010010 120 #define IO_APP_DEBUG_REG_04 0x02010018 121 #define IO_APP_DEBUG_REG_05 0x02010020 122 #define IO_APP_DEBUG_REG_06 0x02010028 123 #define IO_APP_DEBUG_REG_07 0x02010030 124 #define IO_APP_DEBUG_REG_08 0x02010038 125 #define IO_APP_DEBUG_REG_09 0x02010040 126 #define IO_APP_DEBUG_REG_10 0x02010048 127 #define IO_APP_DEBUG_REG_11 0x02010050 128 #define IO_APP_DEBUG_REG_12 0x02010058 129 #define IO_APP_DEBUG_REG_13 0x02010060 130 #define IO_APP_DEBUG_REG_14 0x02010068 131 #define IO_APP_DEBUG_REG_15 0x02010070 132 #define IO_APP_DEBUG_REG_16 0x02010078 133 #define IO_APP_DEBUG_REG_17 0x02010080 134 #define IO_APP_DEBUG_REG_18 0x02010088 135 struct genwqe_reg_io { 136 __u64 num; 137 __u64 val64; 138 }; 139 #define IO_ILLEGAL_VALUE 0xffffffffffffffffull 140 #define DDCB_ACFUNC_SLU 0x00 141 #define DDCB_ACFUNC_APP 0x01 142 #define DDCB_RETC_IDLE 0x0000 143 #define DDCB_RETC_PENDING 0x0101 144 #define DDCB_RETC_COMPLETE 0x0102 145 #define DDCB_RETC_FAULT 0x0104 146 #define DDCB_RETC_ERROR 0x0108 147 #define DDCB_RETC_FORCED_ERROR 0x01ff 148 #define DDCB_RETC_UNEXEC 0x0110 149 #define DDCB_RETC_TERM 0x0120 150 #define DDCB_RETC_RES0 0x0140 151 #define DDCB_RETC_RES1 0x0180 152 #define DDCB_OPT_ECHO_FORCE_NO 0x0000 153 #define DDCB_OPT_ECHO_FORCE_102 0x0001 154 #define DDCB_OPT_ECHO_FORCE_104 0x0002 155 #define DDCB_OPT_ECHO_FORCE_108 0x0003 156 #define DDCB_OPT_ECHO_FORCE_110 0x0004 157 #define DDCB_OPT_ECHO_FORCE_120 0x0005 158 #define DDCB_OPT_ECHO_FORCE_140 0x0006 159 #define DDCB_OPT_ECHO_FORCE_180 0x0007 160 #define DDCB_OPT_ECHO_COPY_NONE (0 << 5) 161 #define DDCB_OPT_ECHO_COPY_ALL (1 << 5) 162 #define SLCMD_ECHO_SYNC 0x00 163 #define SLCMD_MOVE_FLASH 0x06 164 #define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 165 #define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 166 #define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 167 #define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 168 #define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 169 #define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2) 170 #define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3) 171 #define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4) 172 #define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5) 173 enum genwqe_card_state { 174 GENWQE_CARD_UNUSED = 0, 175 GENWQE_CARD_USED = 1, 176 GENWQE_CARD_FATAL_ERROR = 2, 177 GENWQE_CARD_RELOAD_BITSTREAM = 3, 178 GENWQE_CARD_STATE_MAX, 179 }; 180 struct genwqe_bitstream { 181 __u64 data_addr; 182 __u32 size; 183 __u32 crc; 184 __u64 target_addr; 185 __u32 partition; 186 __u32 uid; 187 __u64 slu_id; 188 __u64 app_id; 189 __u16 retc; 190 __u16 attn; 191 __u32 progress; 192 }; 193 #define DDCB_LENGTH 256 194 #define DDCB_ASIV_LENGTH 104 195 #define DDCB_ASIV_LENGTH_ATS 96 196 #define DDCB_ASV_LENGTH 64 197 #define DDCB_FIXUPS 12 198 struct genwqe_debug_data { 199 char driver_version[64]; 200 __u64 slu_unitcfg; 201 __u64 app_unitcfg; 202 __u8 ddcb_before[DDCB_LENGTH]; 203 __u8 ddcb_prev[DDCB_LENGTH]; 204 __u8 ddcb_finished[DDCB_LENGTH]; 205 }; 206 #define ATS_TYPE_DATA 0x0ull 207 #define ATS_TYPE_FLAT_RD 0x4ull 208 #define ATS_TYPE_FLAT_RDWR 0x5ull 209 #define ATS_TYPE_SGL_RD 0x6ull 210 #define ATS_TYPE_SGL_RDWR 0x7ull 211 #define ATS_SET_FLAGS(_struct,_field,_flags) (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8)))) 212 #define ATS_GET_FLAGS(_ats,_byte_offs) (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf) 213 struct genwqe_ddcb_cmd { 214 __u64 next_addr; 215 __u64 flags; 216 __u8 acfunc; 217 __u8 cmd; 218 __u8 asiv_length; 219 __u8 asv_length; 220 __u16 cmdopts; 221 __u16 retc; 222 __u16 attn; 223 __u16 vcrc; 224 __u32 progress; 225 __u64 deque_ts; 226 __u64 cmplt_ts; 227 __u64 disp_ts; 228 __u64 ddata_addr; 229 __u8 asv[DDCB_ASV_LENGTH]; 230 union { 231 struct { 232 __u64 ats; 233 __u8 asiv[DDCB_ASIV_LENGTH_ATS]; 234 }; 235 __u8 __asiv[DDCB_ASIV_LENGTH]; 236 }; 237 }; 238 #define GENWQE_IOC_CODE 0xa5 239 #define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io) 240 #define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io) 241 #define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io) 242 #define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io) 243 #define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io) 244 #define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io) 245 #define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state) 246 struct genwqe_mem { 247 __u64 addr; 248 __u64 size; 249 __u64 direction; 250 __u64 flags; 251 }; 252 #define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem) 253 #define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem) 254 #define GENWQE_EXECUTE_DDCB _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd) 255 #define GENWQE_EXECUTE_RAW_DDCB _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd) 256 #define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream) 257 #define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream) 258 #endif 259