1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_MDP_H_ 20 #define _MSM_MDP_H_ 21 #include <stdint.h> 22 #include <linux/fb.h> 23 #define MSMFB_IOCTL_MAGIC 'm' 24 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 25 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 26 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 27 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 28 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 29 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 30 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 31 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 32 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 33 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 34 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 35 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 36 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 37 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 38 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 39 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 40 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 41 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 42 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 43 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 44 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 45 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 46 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 47 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 48 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 49 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 50 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 51 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 52 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 54 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 55 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 56 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 57 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 58 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 59 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 60 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 61 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 62 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 63 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 64 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 65 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 66 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 67 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 68 #define FB_TYPE_3D_PANEL 0x10101010 69 #define MDP_IMGTYPE2_START 0x10000 70 #define MSMFB_DRIVER_VERSION 0xF9E8D701 71 #define MDP_IMGTYPE_END 0x100 72 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 73 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 74 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 75 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 76 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 77 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 78 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 79 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 80 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 81 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 82 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 83 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 84 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 85 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 86 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 87 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 88 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 89 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 90 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 91 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 92 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 93 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 94 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 95 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 96 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 97 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 98 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 99 #define MDSS_MDP_HW_REV_117 MDSS_MDP_REV(1, 17, 0) 100 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 101 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 102 #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) 103 #define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) 104 enum { 105 NOTIFY_UPDATE_INIT, 106 NOTIFY_UPDATE_DEINIT, 107 NOTIFY_UPDATE_START, 108 NOTIFY_UPDATE_STOP, 109 NOTIFY_UPDATE_POWER_OFF, 110 }; 111 enum { 112 NOTIFY_TYPE_NO_UPDATE, 113 NOTIFY_TYPE_SUSPEND, 114 NOTIFY_TYPE_UPDATE, 115 NOTIFY_TYPE_BL_UPDATE, 116 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 117 }; 118 enum { 119 MDP_RGB_565, 120 MDP_XRGB_8888, 121 MDP_Y_CBCR_H2V2, 122 MDP_Y_CBCR_H2V2_ADRENO, 123 MDP_ARGB_8888, 124 MDP_RGB_888, 125 MDP_Y_CRCB_H2V2, 126 MDP_YCRYCB_H2V1, 127 MDP_CBYCRY_H2V1, 128 MDP_Y_CRCB_H2V1, 129 MDP_Y_CBCR_H2V1, 130 MDP_Y_CRCB_H1V2, 131 MDP_Y_CBCR_H1V2, 132 MDP_RGBA_8888, 133 MDP_BGRA_8888, 134 MDP_RGBX_8888, 135 MDP_Y_CRCB_H2V2_TILE, 136 MDP_Y_CBCR_H2V2_TILE, 137 MDP_Y_CR_CB_H2V2, 138 MDP_Y_CR_CB_GH2V2, 139 MDP_Y_CB_CR_H2V2, 140 MDP_Y_CRCB_H1V1, 141 MDP_Y_CBCR_H1V1, 142 MDP_YCRCB_H1V1, 143 MDP_YCBCR_H1V1, 144 MDP_BGR_565, 145 MDP_BGR_888, 146 MDP_Y_CBCR_H2V2_VENUS, 147 MDP_BGRX_8888, 148 MDP_RGBA_8888_TILE, 149 MDP_ARGB_8888_TILE, 150 MDP_ABGR_8888_TILE, 151 MDP_BGRA_8888_TILE, 152 MDP_RGBX_8888_TILE, 153 MDP_XRGB_8888_TILE, 154 MDP_XBGR_8888_TILE, 155 MDP_BGRX_8888_TILE, 156 MDP_YCBYCR_H2V1, 157 MDP_RGB_565_TILE, 158 MDP_BGR_565_TILE, 159 MDP_ARGB_1555, 160 MDP_RGBA_5551, 161 MDP_ARGB_4444, 162 MDP_RGBA_4444, 163 MDP_RGB_565_UBWC, 164 MDP_RGBA_8888_UBWC, 165 MDP_Y_CBCR_H2V2_UBWC, 166 MDP_RGBX_8888_UBWC, 167 MDP_Y_CRCB_H2V2_VENUS, 168 MDP_IMGTYPE_LIMIT, 169 MDP_RGB_BORDERFILL, 170 MDP_XRGB_1555, 171 MDP_RGBX_5551, 172 MDP_XRGB_4444, 173 MDP_RGBX_4444, 174 MDP_ABGR_1555, 175 MDP_BGRA_5551, 176 MDP_XBGR_1555, 177 MDP_BGRX_5551, 178 MDP_ABGR_4444, 179 MDP_BGRA_4444, 180 MDP_XBGR_4444, 181 MDP_BGRX_4444, 182 MDP_ABGR_8888, 183 MDP_XBGR_8888, 184 MDP_RGBA_1010102, 185 MDP_ARGB_2101010, 186 MDP_RGBX_1010102, 187 MDP_XRGB_2101010, 188 MDP_BGRA_1010102, 189 MDP_ABGR_2101010, 190 MDP_BGRX_1010102, 191 MDP_XBGR_2101010, 192 MDP_RGBA_1010102_UBWC, 193 MDP_RGBX_1010102_UBWC, 194 MDP_Y_CBCR_H2V2_P010, 195 MDP_Y_CBCR_H2V2_TP10_UBWC, 196 MDP_CRYCBY_H2V1, 197 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 198 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 199 MDP_IMGTYPE_LIMIT2 200 }; 201 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 202 enum { 203 PMEM_IMG, 204 FB_IMG, 205 }; 206 enum { 207 HSIC_HUE = 0, 208 HSIC_SAT, 209 HSIC_INT, 210 HSIC_CON, 211 NUM_HSIC_PARAM, 212 }; 213 enum mdss_mdp_max_bw_mode { 214 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 215 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 216 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 217 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 218 }; 219 #define MDSS_MDP_ROT_ONLY 0x80 220 #define MDSS_MDP_RIGHT_MIXER 0x100 221 #define MDSS_MDP_DUAL_PIPE 0x200 222 #define MDP_ROT_NOP 0 223 #define MDP_FLIP_LR 0x1 224 #define MDP_FLIP_UD 0x2 225 #define MDP_ROT_90 0x4 226 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 227 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 228 #define MDP_DITHER 0x8 229 #define MDP_BLUR 0x10 230 #define MDP_BLEND_FG_PREMULT 0x20000 231 #define MDP_IS_FG 0x40000 232 #define MDP_SOLID_FILL 0x00000020 233 #define MDP_VPU_PIPE 0x00000040 234 #define MDP_DEINTERLACE 0x80000000 235 #define MDP_SHARPENING 0x40000000 236 #define MDP_NO_DMA_BARRIER_START 0x20000000 237 #define MDP_NO_DMA_BARRIER_END 0x10000000 238 #define MDP_NO_BLIT 0x08000000 239 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 240 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 241 #define MDP_BLIT_SRC_GEM 0x04000000 242 #define MDP_BLIT_DST_GEM 0x02000000 243 #define MDP_BLIT_NON_CACHED 0x01000000 244 #define MDP_OV_PIPE_SHARE 0x00800000 245 #define MDP_DEINTERLACE_ODD 0x00400000 246 #define MDP_OV_PLAY_NOWAIT 0x00200000 247 #define MDP_SOURCE_ROTATED_90 0x00100000 248 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 249 #define MDP_BACKEND_COMPOSITION 0x00040000 250 #define MDP_BORDERFILL_SUPPORTED 0x00010000 251 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 252 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 253 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 254 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 255 #define MDP_BWC_EN 0x00000400 256 #define MDP_DECIMATION_EN 0x00000800 257 #define MDP_SMP_FORCE_ALLOC 0x00200000 258 #define MDP_TRANSP_NOP 0xffffffff 259 #define MDP_ALPHA_NOP 0xff 260 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 261 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 262 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 263 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 264 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 265 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 266 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 267 #define MDP_DEEP_COLOR_YUV444 0x1 268 #define MDP_DEEP_COLOR_RGB30B 0x2 269 #define MDP_DEEP_COLOR_RGB36B 0x4 270 #define MDP_DEEP_COLOR_RGB48B 0x8 271 struct mdp_rect { 272 uint32_t x; 273 uint32_t y; 274 uint32_t w; 275 uint32_t h; 276 }; 277 struct mdp_img { 278 uint32_t width; 279 uint32_t height; 280 uint32_t format; 281 uint32_t offset; 282 int memory_id; 283 uint32_t priv; 284 }; 285 struct mult_factor { 286 uint32_t numer; 287 uint32_t denom; 288 }; 289 #define MDP_CCS_RGB2YUV 0 290 #define MDP_CCS_YUV2RGB 1 291 #define MDP_CCS_SIZE 9 292 #define MDP_BV_SIZE 3 293 struct mdp_ccs { 294 int direction; 295 uint16_t ccs[MDP_CCS_SIZE]; 296 uint16_t bv[MDP_BV_SIZE]; 297 }; 298 struct mdp_csc { 299 int id; 300 uint32_t csc_mv[9]; 301 uint32_t csc_pre_bv[3]; 302 uint32_t csc_post_bv[3]; 303 uint32_t csc_pre_lv[6]; 304 uint32_t csc_post_lv[6]; 305 }; 306 #define MDP_BLIT_REQ_VERSION 3 307 struct color { 308 uint32_t r; 309 uint32_t g; 310 uint32_t b; 311 uint32_t alpha; 312 }; 313 struct mdp_blit_req { 314 struct mdp_img src; 315 struct mdp_img dst; 316 struct mdp_rect src_rect; 317 struct mdp_rect dst_rect; 318 struct color const_color; 319 uint32_t alpha; 320 uint32_t transp_mask; 321 uint32_t flags; 322 int sharpening_strength; 323 uint8_t color_space; 324 uint32_t fps; 325 }; 326 struct mdp_blit_req_list { 327 uint32_t count; 328 struct mdp_blit_req req[]; 329 }; 330 #define MSMFB_DATA_VERSION 2 331 struct msmfb_data { 332 uint32_t offset; 333 int memory_id; 334 int id; 335 uint32_t flags; 336 uint32_t priv; 337 uint32_t iova; 338 }; 339 #define MSMFB_NEW_REQUEST - 1 340 struct msmfb_overlay_data { 341 uint32_t id; 342 struct msmfb_data data; 343 uint32_t version_key; 344 struct msmfb_data plane1_data; 345 struct msmfb_data plane2_data; 346 struct msmfb_data dst_data; 347 }; 348 struct msmfb_img { 349 uint32_t width; 350 uint32_t height; 351 uint32_t format; 352 }; 353 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 354 struct msmfb_writeback_data { 355 struct msmfb_data buf_info; 356 struct msmfb_img img; 357 }; 358 #define MDP_PP_OPS_ENABLE 0x1 359 #define MDP_PP_OPS_READ 0x2 360 #define MDP_PP_OPS_WRITE 0x4 361 #define MDP_PP_OPS_DISABLE 0x8 362 #define MDP_PP_IGC_FLAG_ROM0 0x10 363 #define MDP_PP_IGC_FLAG_ROM1 0x20 364 #define MDSS_PP_DSPP_CFG 0x000 365 #define MDSS_PP_SSPP_CFG 0x100 366 #define MDSS_PP_LM_CFG 0x200 367 #define MDSS_PP_WB_CFG 0x300 368 #define MDSS_PP_ARG_MASK 0x3C00 369 #define MDSS_PP_ARG_NUM 4 370 #define MDSS_PP_ARG_SHIFT 10 371 #define MDSS_PP_LOCATION_MASK 0x0300 372 #define MDSS_PP_LOGICAL_MASK 0x00FF 373 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 374 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 375 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 376 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 377 struct mdp_qseed_cfg { 378 uint32_t table_num; 379 uint32_t ops; 380 uint32_t len; 381 uint32_t * data; 382 }; 383 struct mdp_sharp_cfg { 384 uint32_t flags; 385 uint32_t strength; 386 uint32_t edge_thr; 387 uint32_t smooth_thr; 388 uint32_t noise_thr; 389 }; 390 struct mdp_qseed_cfg_data { 391 uint32_t block; 392 struct mdp_qseed_cfg qseed_data; 393 }; 394 #define MDP_OVERLAY_PP_CSC_CFG 0x1 395 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 396 #define MDP_OVERLAY_PP_PA_CFG 0x4 397 #define MDP_OVERLAY_PP_IGC_CFG 0x8 398 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 399 #define MDP_OVERLAY_PP_HIST_CFG 0x20 400 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 401 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 402 #define MDP_OVERLAY_PP_PCC_CFG 0x100 403 #define MDP_CSC_FLAG_ENABLE 0x1 404 #define MDP_CSC_FLAG_YUV_IN 0x2 405 #define MDP_CSC_FLAG_YUV_OUT 0x4 406 #define MDP_CSC_MATRIX_COEFF_SIZE 9 407 #define MDP_CSC_CLAMP_SIZE 6 408 #define MDP_CSC_BIAS_SIZE 3 409 struct mdp_csc_cfg { 410 uint32_t flags; 411 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 412 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 413 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 414 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 415 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 416 }; 417 struct mdp_csc_cfg_data { 418 uint32_t block; 419 struct mdp_csc_cfg csc_data; 420 }; 421 struct mdp_pa_cfg { 422 uint32_t flags; 423 uint32_t hue_adj; 424 uint32_t sat_adj; 425 uint32_t val_adj; 426 uint32_t cont_adj; 427 }; 428 struct mdp_pa_mem_col_cfg { 429 uint32_t color_adjust_p0; 430 uint32_t color_adjust_p1; 431 uint32_t hue_region; 432 uint32_t sat_region; 433 uint32_t val_region; 434 }; 435 #define MDP_SIX_ZONE_LUT_SIZE 384 436 #define MDP_PP_PA_HUE_ENABLE 0x10 437 #define MDP_PP_PA_SAT_ENABLE 0x20 438 #define MDP_PP_PA_VAL_ENABLE 0x40 439 #define MDP_PP_PA_CONT_ENABLE 0x80 440 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 441 #define MDP_PP_PA_SKIN_ENABLE 0x200 442 #define MDP_PP_PA_SKY_ENABLE 0x400 443 #define MDP_PP_PA_FOL_ENABLE 0x800 444 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 445 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 446 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 447 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 448 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 449 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 450 #define MDP_PP_PA_HUE_MASK 0x1000 451 #define MDP_PP_PA_SAT_MASK 0x2000 452 #define MDP_PP_PA_VAL_MASK 0x4000 453 #define MDP_PP_PA_CONT_MASK 0x8000 454 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 455 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 456 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 457 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 458 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 459 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 460 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 461 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 462 #define MDP_PP_PA_LEFT_HOLD 0x1 463 #define MDP_PP_PA_RIGHT_HOLD 0x2 464 struct mdp_pa_v2_data { 465 uint32_t flags; 466 uint32_t global_hue_adj; 467 uint32_t global_sat_adj; 468 uint32_t global_val_adj; 469 uint32_t global_cont_adj; 470 struct mdp_pa_mem_col_cfg skin_cfg; 471 struct mdp_pa_mem_col_cfg sky_cfg; 472 struct mdp_pa_mem_col_cfg fol_cfg; 473 uint32_t six_zone_len; 474 uint32_t six_zone_thresh; 475 uint32_t * six_zone_curve_p0; 476 uint32_t * six_zone_curve_p1; 477 }; 478 struct mdp_pa_mem_col_data_v1_7 { 479 uint32_t color_adjust_p0; 480 uint32_t color_adjust_p1; 481 uint32_t color_adjust_p2; 482 uint32_t blend_gain; 483 uint8_t sat_hold; 484 uint8_t val_hold; 485 uint32_t hue_region; 486 uint32_t sat_region; 487 uint32_t val_region; 488 }; 489 struct mdp_pa_data_v1_7 { 490 uint32_t mode; 491 uint32_t global_hue_adj; 492 uint32_t global_sat_adj; 493 uint32_t global_val_adj; 494 uint32_t global_cont_adj; 495 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 496 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 497 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 498 uint32_t six_zone_thresh; 499 uint32_t six_zone_adj_p0; 500 uint32_t six_zone_adj_p1; 501 uint8_t six_zone_sat_hold; 502 uint8_t six_zone_val_hold; 503 uint32_t six_zone_len; 504 uint32_t * six_zone_curve_p0; 505 uint32_t * six_zone_curve_p1; 506 }; 507 struct mdp_pa_v2_cfg_data { 508 uint32_t version; 509 uint32_t block; 510 uint32_t flags; 511 struct mdp_pa_v2_data pa_v2_data; 512 void * cfg_payload; 513 }; 514 enum { 515 mdp_igc_rec601 = 1, 516 mdp_igc_rec709, 517 mdp_igc_srgb, 518 mdp_igc_custom, 519 mdp_igc_rec_max, 520 }; 521 struct mdp_igc_lut_data { 522 uint32_t block; 523 uint32_t version; 524 uint32_t len, ops; 525 uint32_t * c0_c1_data; 526 uint32_t * c2_data; 527 void * cfg_payload; 528 }; 529 struct mdp_igc_lut_data_v1_7 { 530 uint32_t table_fmt; 531 uint32_t len; 532 uint32_t * c0_c1_data; 533 uint32_t * c2_data; 534 }; 535 struct mdp_igc_lut_data_payload { 536 uint32_t table_fmt; 537 uint32_t len; 538 uint64_t c0_c1_data; 539 uint64_t c2_data; 540 uint32_t strength; 541 }; 542 struct mdp_histogram_cfg { 543 uint32_t ops; 544 uint32_t block; 545 uint8_t frame_cnt; 546 uint8_t bit_mask; 547 uint16_t num_bins; 548 }; 549 struct mdp_hist_lut_data_v1_7 { 550 uint32_t len; 551 uint32_t * data; 552 }; 553 struct mdp_hist_lut_data { 554 uint32_t block; 555 uint32_t version; 556 uint32_t hist_lut_first; 557 uint32_t ops; 558 uint32_t len; 559 uint32_t * data; 560 void * cfg_payload; 561 }; 562 struct mdp_pcc_coeff { 563 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 564 }; 565 struct mdp_pcc_coeff_v1_7 { 566 uint32_t c, r, g, b, rg, gb, rb, rgb; 567 }; 568 struct mdp_pcc_data_v1_7 { 569 struct mdp_pcc_coeff_v1_7 r, g, b; 570 }; 571 struct mdp_pcc_cfg_data { 572 uint32_t version; 573 uint32_t block; 574 uint32_t ops; 575 struct mdp_pcc_coeff r, g, b; 576 void * cfg_payload; 577 }; 578 enum { 579 mdp_lut_igc, 580 mdp_lut_pgc, 581 mdp_lut_hist, 582 mdp_lut_rgb, 583 mdp_lut_max, 584 }; 585 struct mdp_overlay_pp_params { 586 uint32_t config_ops; 587 struct mdp_csc_cfg csc_cfg; 588 struct mdp_qseed_cfg qseed_cfg[2]; 589 struct mdp_pa_cfg pa_cfg; 590 struct mdp_pa_v2_data pa_v2_cfg; 591 struct mdp_igc_lut_data igc_cfg; 592 struct mdp_sharp_cfg sharp_cfg; 593 struct mdp_histogram_cfg hist_cfg; 594 struct mdp_hist_lut_data hist_lut_cfg; 595 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 596 struct mdp_pcc_cfg_data pcc_cfg_data; 597 }; 598 enum mdss_mdp_blend_op { 599 BLEND_OP_NOT_DEFINED = 0, 600 BLEND_OP_OPAQUE, 601 BLEND_OP_PREMULTIPLIED, 602 BLEND_OP_COVERAGE, 603 BLEND_OP_MAX, 604 }; 605 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 606 #define MAX_PLANES 4 607 struct mdp_scale_data { 608 uint8_t enable_pxl_ext; 609 int init_phase_x[MAX_PLANES]; 610 int phase_step_x[MAX_PLANES]; 611 int init_phase_y[MAX_PLANES]; 612 int phase_step_y[MAX_PLANES]; 613 int num_ext_pxls_left[MAX_PLANES]; 614 int num_ext_pxls_right[MAX_PLANES]; 615 int num_ext_pxls_top[MAX_PLANES]; 616 int num_ext_pxls_btm[MAX_PLANES]; 617 int left_ftch[MAX_PLANES]; 618 int left_rpt[MAX_PLANES]; 619 int right_ftch[MAX_PLANES]; 620 int right_rpt[MAX_PLANES]; 621 int top_rpt[MAX_PLANES]; 622 int btm_rpt[MAX_PLANES]; 623 int top_ftch[MAX_PLANES]; 624 int btm_ftch[MAX_PLANES]; 625 uint32_t roi_w[MAX_PLANES]; 626 }; 627 enum mdp_overlay_pipe_type { 628 PIPE_TYPE_AUTO = 0, 629 PIPE_TYPE_VIG, 630 PIPE_TYPE_RGB, 631 PIPE_TYPE_DMA, 632 PIPE_TYPE_CURSOR, 633 PIPE_TYPE_MAX, 634 }; 635 struct mdp_overlay { 636 struct msmfb_img src; 637 struct mdp_rect src_rect; 638 struct mdp_rect dst_rect; 639 uint32_t z_order; 640 uint32_t is_fg; 641 uint32_t alpha; 642 uint32_t blend_op; 643 uint32_t transp_mask; 644 uint32_t flags; 645 uint32_t pipe_type; 646 uint32_t id; 647 uint8_t priority; 648 uint32_t user_data[6]; 649 uint32_t bg_color; 650 uint8_t horz_deci; 651 uint8_t vert_deci; 652 struct mdp_overlay_pp_params overlay_pp_cfg; 653 struct mdp_scale_data scale; 654 uint8_t color_space; 655 uint32_t frame_rate; 656 }; 657 struct msmfb_overlay_3d { 658 uint32_t is_3d; 659 uint32_t width; 660 uint32_t height; 661 }; 662 struct msmfb_overlay_blt { 663 uint32_t enable; 664 uint32_t offset; 665 uint32_t width; 666 uint32_t height; 667 uint32_t bpp; 668 }; 669 struct mdp_histogram { 670 uint32_t frame_cnt; 671 uint32_t bin_cnt; 672 uint32_t * r; 673 uint32_t * g; 674 uint32_t * b; 675 }; 676 #define MISR_CRC_BATCH_SIZE 32 677 enum { 678 DISPLAY_MISR_EDP, 679 DISPLAY_MISR_DSI0, 680 DISPLAY_MISR_DSI1, 681 DISPLAY_MISR_HDMI, 682 DISPLAY_MISR_LCDC, 683 DISPLAY_MISR_MDP, 684 DISPLAY_MISR_ATV, 685 DISPLAY_MISR_DSI_CMD, 686 DISPLAY_MISR_MAX 687 }; 688 enum { 689 MISR_OP_NONE, 690 MISR_OP_SFM, 691 MISR_OP_MFM, 692 MISR_OP_BM, 693 MISR_OP_MAX 694 }; 695 struct mdp_misr { 696 uint32_t block_id; 697 uint32_t frame_count; 698 uint32_t crc_op_mode; 699 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 700 }; 701 enum { 702 MDP_BLOCK_RESERVED = 0, 703 MDP_BLOCK_OVERLAY_0, 704 MDP_BLOCK_OVERLAY_1, 705 MDP_BLOCK_VG_1, 706 MDP_BLOCK_VG_2, 707 MDP_BLOCK_RGB_1, 708 MDP_BLOCK_RGB_2, 709 MDP_BLOCK_DMA_P, 710 MDP_BLOCK_DMA_S, 711 MDP_BLOCK_DMA_E, 712 MDP_BLOCK_OVERLAY_2, 713 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 714 MDP_LOGICAL_BLOCK_DISP_1, 715 MDP_LOGICAL_BLOCK_DISP_2, 716 MDP_BLOCK_MAX, 717 }; 718 struct mdp_histogram_start_req { 719 uint32_t block; 720 uint8_t frame_cnt; 721 uint8_t bit_mask; 722 uint16_t num_bins; 723 }; 724 struct mdp_histogram_data { 725 uint32_t block; 726 uint32_t bin_cnt; 727 uint32_t * c0; 728 uint32_t * c1; 729 uint32_t * c2; 730 uint32_t * extra_info; 731 }; 732 #define GC_LUT_ENTRIES_V1_7 512 733 struct mdp_ar_gc_lut_data { 734 uint32_t x_start; 735 uint32_t slope; 736 uint32_t offset; 737 }; 738 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 739 struct mdp_pgc_lut_data { 740 uint32_t version; 741 uint32_t block; 742 uint32_t flags; 743 uint8_t num_r_stages; 744 uint8_t num_g_stages; 745 uint8_t num_b_stages; 746 struct mdp_ar_gc_lut_data * r_data; 747 struct mdp_ar_gc_lut_data * g_data; 748 struct mdp_ar_gc_lut_data * b_data; 749 void * cfg_payload; 750 }; 751 #define PGC_LUT_ENTRIES 1024 752 struct mdp_pgc_lut_data_v1_7 { 753 uint32_t len; 754 uint32_t * c0_data; 755 uint32_t * c1_data; 756 uint32_t * c2_data; 757 }; 758 struct mdp_rgb_lut_data { 759 uint32_t flags; 760 uint32_t lut_type; 761 struct fb_cmap cmap; 762 }; 763 enum { 764 mdp_rgb_lut_gc, 765 mdp_rgb_lut_hist, 766 }; 767 struct mdp_lut_cfg_data { 768 uint32_t lut_type; 769 union { 770 struct mdp_igc_lut_data igc_lut_data; 771 struct mdp_pgc_lut_data pgc_lut_data; 772 struct mdp_hist_lut_data hist_lut_data; 773 struct mdp_rgb_lut_data rgb_lut_data; 774 } data; 775 }; 776 struct mdp_bl_scale_data { 777 uint32_t min_lvl; 778 uint32_t scale; 779 }; 780 struct mdp_pa_cfg_data { 781 uint32_t block; 782 struct mdp_pa_cfg pa_data; 783 }; 784 #define MDP_DITHER_DATA_V1_7_SZ 16 785 struct mdp_dither_data_v1_7 { 786 uint32_t g_y_depth; 787 uint32_t r_cr_depth; 788 uint32_t b_cb_depth; 789 uint32_t len; 790 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 791 uint32_t temporal_en; 792 }; 793 struct mdp_pa_dither_data { 794 uint64_t data_flags; 795 uint32_t matrix_sz; 796 uint64_t matrix_data; 797 uint32_t strength; 798 uint32_t offset_en; 799 }; 800 struct mdp_dither_cfg_data { 801 uint32_t version; 802 uint32_t block; 803 uint32_t flags; 804 uint32_t mode; 805 uint32_t g_y_depth; 806 uint32_t r_cr_depth; 807 uint32_t b_cb_depth; 808 void * cfg_payload; 809 }; 810 #define MDP_GAMUT_TABLE_NUM 8 811 #define MDP_GAMUT_TABLE_NUM_V1_7 4 812 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 813 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 814 #define MDP_GAMUT_SCALE_OFF_SZ 16 815 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 816 struct mdp_gamut_cfg_data { 817 uint32_t block; 818 uint32_t flags; 819 uint32_t version; 820 uint32_t gamut_first; 821 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 822 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 823 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 824 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 825 void * cfg_payload; 826 }; 827 enum { 828 mdp_gamut_fine_mode = 0x1, 829 mdp_gamut_coarse_mode, 830 }; 831 struct mdp_gamut_data_v1_7 { 832 uint32_t mode; 833 uint32_t map_en; 834 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 835 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 836 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 837 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 838 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 839 }; 840 struct mdp_calib_config_data { 841 uint32_t ops; 842 uint32_t addr; 843 uint32_t data; 844 }; 845 struct mdp_calib_config_buffer { 846 uint32_t ops; 847 uint32_t size; 848 uint32_t * buffer; 849 }; 850 struct mdp_calib_dcm_state { 851 uint32_t ops; 852 uint32_t dcm_state; 853 }; 854 enum { 855 DCM_UNINIT, 856 DCM_UNBLANK, 857 DCM_ENTER, 858 DCM_EXIT, 859 DCM_BLANK, 860 DTM_ENTER, 861 DTM_EXIT, 862 }; 863 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 864 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 865 #define MDSS_PP_SPLIT_MASK 0x30000000 866 #define MDSS_MAX_BL_BRIGHTNESS 255 867 #define AD_BL_LIN_LEN 256 868 #define AD_BL_ATT_LUT_LEN 33 869 #define MDSS_AD_MODE_AUTO_BL 0x0 870 #define MDSS_AD_MODE_AUTO_STR 0x1 871 #define MDSS_AD_MODE_TARG_STR 0x3 872 #define MDSS_AD_MODE_MAN_STR 0x7 873 #define MDSS_AD_MODE_CALIB 0xF 874 #define MDP_PP_AD_INIT 0x10 875 #define MDP_PP_AD_CFG 0x20 876 struct mdss_ad_init { 877 uint32_t asym_lut[33]; 878 uint32_t color_corr_lut[33]; 879 uint8_t i_control[2]; 880 uint16_t black_lvl; 881 uint16_t white_lvl; 882 uint8_t var; 883 uint8_t limit_ampl; 884 uint8_t i_dither; 885 uint8_t slope_max; 886 uint8_t slope_min; 887 uint8_t dither_ctl; 888 uint8_t format; 889 uint8_t auto_size; 890 uint16_t frame_w; 891 uint16_t frame_h; 892 uint8_t logo_v; 893 uint8_t logo_h; 894 uint32_t alpha; 895 uint32_t alpha_base; 896 uint32_t al_thresh; 897 uint32_t bl_lin_len; 898 uint32_t bl_att_len; 899 uint32_t * bl_lin; 900 uint32_t * bl_lin_inv; 901 uint32_t * bl_att_lut; 902 }; 903 #define MDSS_AD_BL_CTRL_MODE_EN 1 904 #define MDSS_AD_BL_CTRL_MODE_DIS 0 905 struct mdss_ad_cfg { 906 uint32_t mode; 907 uint32_t al_calib_lut[33]; 908 uint16_t backlight_min; 909 uint16_t backlight_max; 910 uint16_t backlight_scale; 911 uint16_t amb_light_min; 912 uint16_t filter[2]; 913 uint16_t calib[4]; 914 uint8_t strength_limit; 915 uint8_t t_filter_recursion; 916 uint16_t stab_itr; 917 uint32_t bl_ctrl_mode; 918 }; 919 struct mdss_ad_bl_cfg { 920 uint32_t bl_min_delta; 921 uint32_t bl_low_limit; 922 }; 923 struct mdss_ad_init_cfg { 924 uint32_t ops; 925 union { 926 struct mdss_ad_init init; 927 struct mdss_ad_cfg cfg; 928 } params; 929 }; 930 struct mdss_ad_input { 931 uint32_t mode; 932 union { 933 uint32_t amb_light; 934 uint32_t strength; 935 uint32_t calib_bl; 936 } in; 937 uint32_t output; 938 }; 939 #define MDSS_CALIB_MODE_BL 0x1 940 struct mdss_calib_cfg { 941 uint32_t ops; 942 uint32_t calib_mask; 943 }; 944 enum { 945 mdp_op_pcc_cfg, 946 mdp_op_csc_cfg, 947 mdp_op_lut_cfg, 948 mdp_op_qseed_cfg, 949 mdp_bl_scale_cfg, 950 mdp_op_pa_cfg, 951 mdp_op_pa_v2_cfg, 952 mdp_op_dither_cfg, 953 mdp_op_gamut_cfg, 954 mdp_op_calib_cfg, 955 mdp_op_ad_cfg, 956 mdp_op_ad_input, 957 mdp_op_calib_mode, 958 mdp_op_calib_buffer, 959 mdp_op_calib_dcm_state, 960 mdp_op_max, 961 mdp_op_pa_dither_cfg, 962 mdp_op_ad_bl_cfg, 963 mdp_op_pp_max = 255, 964 }; 965 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 966 #define mdp_op_pp_max mdp_op_pp_max 967 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 968 enum { 969 WB_FORMAT_NV12, 970 WB_FORMAT_RGB_565, 971 WB_FORMAT_RGB_888, 972 WB_FORMAT_xRGB_8888, 973 WB_FORMAT_ARGB_8888, 974 WB_FORMAT_BGRA_8888, 975 WB_FORMAT_BGRX_8888, 976 WB_FORMAT_ARGB_8888_INPUT_ALPHA 977 }; 978 struct msmfb_mdp_pp { 979 uint32_t op; 980 union { 981 struct mdp_pcc_cfg_data pcc_cfg_data; 982 struct mdp_csc_cfg_data csc_cfg_data; 983 struct mdp_lut_cfg_data lut_cfg_data; 984 struct mdp_qseed_cfg_data qseed_cfg_data; 985 struct mdp_bl_scale_data bl_scale_data; 986 struct mdp_pa_cfg_data pa_cfg_data; 987 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 988 struct mdp_dither_cfg_data dither_cfg_data; 989 struct mdp_gamut_cfg_data gamut_cfg_data; 990 struct mdp_calib_config_data calib_cfg; 991 struct mdss_ad_init_cfg ad_init_cfg; 992 struct mdss_calib_cfg mdss_calib_cfg; 993 struct mdss_ad_input ad_input; 994 struct mdp_calib_config_buffer calib_buffer; 995 struct mdp_calib_dcm_state calib_dcm; 996 struct mdss_ad_bl_cfg ad_bl_cfg; 997 } data; 998 }; 999 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1000 enum { 1001 metadata_op_none, 1002 metadata_op_base_blend, 1003 metadata_op_frame_rate, 1004 metadata_op_vic, 1005 metadata_op_wb_format, 1006 metadata_op_wb_secure, 1007 metadata_op_get_caps, 1008 metadata_op_crc, 1009 metadata_op_get_ion_fd, 1010 metadata_op_max 1011 }; 1012 struct mdp_blend_cfg { 1013 uint32_t is_premultiplied; 1014 }; 1015 struct mdp_mixer_cfg { 1016 uint32_t writeback_format; 1017 uint32_t alpha; 1018 }; 1019 struct mdss_hw_caps { 1020 uint32_t mdp_rev; 1021 uint8_t rgb_pipes; 1022 uint8_t vig_pipes; 1023 uint8_t dma_pipes; 1024 uint8_t max_smp_cnt; 1025 uint8_t smp_per_pipe; 1026 uint32_t features; 1027 }; 1028 struct msmfb_metadata { 1029 uint32_t op; 1030 uint32_t flags; 1031 union { 1032 struct mdp_misr misr_request; 1033 struct mdp_blend_cfg blend_cfg; 1034 struct mdp_mixer_cfg mixer_cfg; 1035 uint32_t panel_frame_rate; 1036 uint32_t video_info_code; 1037 struct mdss_hw_caps caps; 1038 uint8_t secure_en; 1039 int fbmem_ionfd; 1040 } data; 1041 }; 1042 #define MDP_MAX_FENCE_FD 32 1043 #define MDP_BUF_SYNC_FLAG_WAIT 1 1044 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1045 struct mdp_buf_sync { 1046 uint32_t flags; 1047 uint32_t acq_fen_fd_cnt; 1048 uint32_t session_id; 1049 int * acq_fen_fd; 1050 int * rel_fen_fd; 1051 int * retire_fen_fd; 1052 }; 1053 struct mdp_async_blit_req_list { 1054 struct mdp_buf_sync sync; 1055 uint32_t count; 1056 struct mdp_blit_req req[]; 1057 }; 1058 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1059 struct mdp_display_commit { 1060 uint32_t flags; 1061 uint32_t wait_for_finish; 1062 struct fb_var_screeninfo var; 1063 struct mdp_rect l_roi; 1064 struct mdp_rect r_roi; 1065 }; 1066 struct mdp_overlay_list { 1067 uint32_t num_overlays; 1068 struct mdp_overlay * * overlay_list; 1069 uint32_t flags; 1070 uint32_t processed_overlays; 1071 }; 1072 struct mdp_page_protection { 1073 uint32_t page_protection; 1074 }; 1075 struct mdp_mixer_info { 1076 int pndx; 1077 int pnum; 1078 int ptype; 1079 int mixer_num; 1080 int z_order; 1081 }; 1082 #define MAX_PIPE_PER_MIXER 7 1083 struct msmfb_mixer_info_req { 1084 int mixer_num; 1085 int cnt; 1086 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1087 }; 1088 enum { 1089 DISPLAY_SUBSYSTEM_ID, 1090 ROTATOR_SUBSYSTEM_ID, 1091 }; 1092 enum { 1093 MDP_IOMMU_DOMAIN_CP, 1094 MDP_IOMMU_DOMAIN_NS, 1095 }; 1096 enum { 1097 MDP_WRITEBACK_MIRROR_OFF, 1098 MDP_WRITEBACK_MIRROR_ON, 1099 MDP_WRITEBACK_MIRROR_PAUSE, 1100 MDP_WRITEBACK_MIRROR_RESUME, 1101 }; 1102 enum mdp_color_space { 1103 MDP_CSC_ITU_R_601, 1104 MDP_CSC_ITU_R_601_FR, 1105 MDP_CSC_ITU_R_709, 1106 }; 1107 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1108 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1109 enum { 1110 mdp_igc_v1_7 = 1, 1111 mdp_igc_vmax, 1112 mdp_hist_lut_v1_7, 1113 mdp_hist_lut_vmax, 1114 mdp_pgc_v1_7, 1115 mdp_pgc_vmax, 1116 mdp_dither_v1_7, 1117 mdp_dither_vmax, 1118 mdp_gamut_v1_7, 1119 mdp_gamut_vmax, 1120 mdp_pa_v1_7, 1121 mdp_pa_vmax, 1122 mdp_pcc_v1_7, 1123 mdp_pcc_vmax, 1124 mdp_pp_legacy, 1125 mdp_dither_pa_v1_7, 1126 mdp_igc_v3, 1127 mdp_pp_unknown = 255 1128 }; 1129 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1130 #define mdp_pp_unknown mdp_pp_unknown 1131 #define mdp_igc_v3 mdp_igc_v3 1132 enum { 1133 IGC = 1, 1134 PCC, 1135 GC, 1136 PA, 1137 GAMUT, 1138 DITHER, 1139 QSEED, 1140 HIST_LUT, 1141 HIST, 1142 PP_FEATURE_MAX, 1143 PA_DITHER, 1144 PP_MAX_FEATURES = 25, 1145 }; 1146 #define PA_DITHER PA_DITHER 1147 #define PP_MAX_FEATURES PP_MAX_FEATURES 1148 struct mdp_pp_feature_version { 1149 uint32_t pp_feature; 1150 uint32_t version_info; 1151 }; 1152 #endif 1153