1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _MSM_DRM_PP_H_ 8 #define _MSM_DRM_PP_H_ 9 #include <linux/types.h> 10 struct drm_msm_pcc_coeff { 11 __u32 c; 12 __u32 r; 13 __u32 g; 14 __u32 b; 15 __u32 rg; 16 __u32 gb; 17 __u32 rb; 18 __u32 rgb; 19 }; 20 #define DRM_MSM_PCC3 21 #define NUM_STRUCT_MASK (0xFUL << 60) 22 struct drm_msm_pcc { 23 __u64 flags; 24 struct drm_msm_pcc_coeff r; 25 struct drm_msm_pcc_coeff g; 26 struct drm_msm_pcc_coeff b; 27 __u32 r_rr; 28 __u32 r_gg; 29 __u32 r_bb; 30 __u32 g_rr; 31 __u32 g_gg; 32 __u32 g_bb; 33 __u32 b_rr; 34 __u32 b_gg; 35 __u32 b_bb; 36 }; 37 #define PA_VLUT_SIZE 256 38 struct drm_msm_pa_vlut { 39 __u64 flags; 40 __u32 val[PA_VLUT_SIZE]; 41 }; 42 #define PA_HSIC_HUE_ENABLE (1 << 0) 43 #define PA_HSIC_SAT_ENABLE (1 << 1) 44 #define PA_HSIC_VAL_ENABLE (1 << 2) 45 #define PA_HSIC_CONT_ENABLE (1 << 3) 46 #define DRM_MSM_PA_HSIC 47 struct drm_msm_pa_hsic { 48 __u64 flags; 49 __u32 hue; 50 __u32 saturation; 51 __u32 value; 52 __u32 contrast; 53 }; 54 #define MEMCOL_PROT_HUE (1 << 0) 55 #define MEMCOL_PROT_SAT (1 << 1) 56 #define MEMCOL_PROT_VAL (1 << 2) 57 #define MEMCOL_PROT_CONT (1 << 3) 58 #define MEMCOL_PROT_SIXZONE (1 << 4) 59 #define MEMCOL_PROT_BLEND (1 << 5) 60 #define DRM_MSM_MEMCOL 61 struct drm_msm_memcol { 62 __u64 prot_flags; 63 __u32 color_adjust_p0; 64 __u32 color_adjust_p1; 65 __u32 color_adjust_p2; 66 __u32 blend_gain; 67 __u32 sat_hold; 68 __u32 val_hold; 69 __u32 hue_region; 70 __u32 sat_region; 71 __u32 val_region; 72 __u64 flags; 73 }; 74 #define DRM_MSM_SIXZONE 75 #define SIXZONE_LUT_SIZE 384 76 #define SIXZONE_HUE_ENABLE (1 << 0) 77 #define SIXZONE_SAT_ENABLE (1 << 1) 78 #define SIXZONE_VAL_ENABLE (1 << 2) 79 struct drm_msm_sixzone_curve { 80 __u32 p1; 81 __u32 p0; 82 }; 83 struct drm_msm_sixzone { 84 __u64 flags; 85 __u32 threshold; 86 __u32 adjust_p0; 87 __u32 adjust_p1; 88 __u32 sat_hold; 89 __u32 val_hold; 90 struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE]; 91 }; 92 #define GAMUT_3D_MODE_17 1 93 #define GAMUT_3D_MODE_5 2 94 #define GAMUT_3D_MODE_13 3 95 #define GAMUT_3D_MODE17_TBL_SZ 1229 96 #define GAMUT_3D_MODE5_TBL_SZ 32 97 #define GAMUT_3D_MODE13_TBL_SZ 550 98 #define GAMUT_3D_SCALE_OFF_SZ 16 99 #define GAMUT_3D_SCALEB_OFF_SZ 12 100 #define GAMUT_3D_TBL_NUM 4 101 #define GAMUT_3D_SCALE_OFF_TBL_NUM 3 102 #define GAMUT_3D_MAP_EN (1 << 0) 103 struct drm_msm_3d_col { 104 __u32 c2_c1; 105 __u32 c0; 106 }; 107 struct drm_msm_3d_gamut { 108 __u64 flags; 109 __u32 mode; 110 __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; 111 struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; 112 }; 113 #define PGC_TBL_LEN 512 114 #define PGC_8B_ROUND (1 << 0) 115 struct drm_msm_pgc_lut { 116 __u64 flags; 117 __u32 c0[PGC_TBL_LEN]; 118 __u32 c1[PGC_TBL_LEN]; 119 __u32 c2[PGC_TBL_LEN]; 120 }; 121 #define IGC_TBL_LEN 256 122 #define IGC_DITHER_ENABLE (1 << 0) 123 struct drm_msm_igc_lut { 124 __u64 flags; 125 __u32 c0[IGC_TBL_LEN]; 126 __u32 c1[IGC_TBL_LEN]; 127 __u32 c2[IGC_TBL_LEN]; 128 __u32 strength; 129 __u32 c0_last; 130 __u32 c1_last; 131 __u32 c2_last; 132 }; 133 #define LAST_LUT 2 134 #define HIST_V_SIZE 256 135 struct drm_msm_hist { 136 __u64 flags; 137 __u32 data[HIST_V_SIZE]; 138 }; 139 #define AD4_LUT_GRP0_SIZE 33 140 #define AD4_LUT_GRP1_SIZE 32 141 struct drm_msm_ad4_init { 142 __u32 init_param_001[AD4_LUT_GRP0_SIZE]; 143 __u32 init_param_002[AD4_LUT_GRP0_SIZE]; 144 __u32 init_param_003[AD4_LUT_GRP0_SIZE]; 145 __u32 init_param_004[AD4_LUT_GRP0_SIZE]; 146 __u32 init_param_005[AD4_LUT_GRP1_SIZE]; 147 __u32 init_param_006[AD4_LUT_GRP1_SIZE]; 148 __u32 init_param_007[AD4_LUT_GRP0_SIZE]; 149 __u32 init_param_008[AD4_LUT_GRP0_SIZE]; 150 __u32 init_param_009; 151 __u32 init_param_010; 152 __u32 init_param_011; 153 __u32 init_param_012; 154 __u32 init_param_013; 155 __u32 init_param_014; 156 __u32 init_param_015; 157 __u32 init_param_016; 158 __u32 init_param_017; 159 __u32 init_param_018; 160 __u32 init_param_019; 161 __u32 init_param_020; 162 __u32 init_param_021; 163 __u32 init_param_022; 164 __u32 init_param_023; 165 __u32 init_param_024; 166 __u32 init_param_025; 167 __u32 init_param_026; 168 __u32 init_param_027; 169 __u32 init_param_028; 170 __u32 init_param_029; 171 __u32 init_param_030; 172 __u32 init_param_031; 173 __u32 init_param_032; 174 __u32 init_param_033; 175 __u32 init_param_034; 176 __u32 init_param_035; 177 __u32 init_param_036; 178 __u32 init_param_037; 179 __u32 init_param_038; 180 __u32 init_param_039; 181 __u32 init_param_040; 182 __u32 init_param_041; 183 __u32 init_param_042; 184 __u32 init_param_043; 185 __u32 init_param_044; 186 __u32 init_param_045; 187 __u32 init_param_046; 188 __u32 init_param_047; 189 __u32 init_param_048; 190 __u32 init_param_049; 191 __u32 init_param_050; 192 __u32 init_param_051; 193 __u32 init_param_052; 194 __u32 init_param_053; 195 __u32 init_param_054; 196 __u32 init_param_055; 197 __u32 init_param_056; 198 __u32 init_param_057; 199 __u32 init_param_058; 200 __u32 init_param_059; 201 __u32 init_param_060; 202 __u32 init_param_061; 203 __u32 init_param_062; 204 __u32 init_param_063; 205 __u32 init_param_064; 206 __u32 init_param_065; 207 __u32 init_param_066; 208 __u32 init_param_067; 209 __u32 init_param_068; 210 __u32 init_param_069; 211 __u32 init_param_070; 212 __u32 init_param_071; 213 __u32 init_param_072; 214 __u32 init_param_073; 215 __u32 init_param_074; 216 __u32 init_param_075; 217 }; 218 struct drm_msm_ad4_cfg { 219 __u32 cfg_param_001; 220 __u32 cfg_param_002; 221 __u32 cfg_param_003; 222 __u32 cfg_param_004; 223 __u32 cfg_param_005; 224 __u32 cfg_param_006; 225 __u32 cfg_param_007; 226 __u32 cfg_param_008; 227 __u32 cfg_param_009; 228 __u32 cfg_param_010; 229 __u32 cfg_param_011; 230 __u32 cfg_param_012; 231 __u32 cfg_param_013; 232 __u32 cfg_param_014; 233 __u32 cfg_param_015; 234 __u32 cfg_param_016; 235 __u32 cfg_param_017; 236 __u32 cfg_param_018; 237 __u32 cfg_param_019; 238 __u32 cfg_param_020; 239 __u32 cfg_param_021; 240 __u32 cfg_param_022; 241 __u32 cfg_param_023; 242 __u32 cfg_param_024; 243 __u32 cfg_param_025; 244 __u32 cfg_param_026; 245 __u32 cfg_param_027; 246 __u32 cfg_param_028; 247 __u32 cfg_param_029; 248 __u32 cfg_param_030; 249 __u32 cfg_param_031; 250 __u32 cfg_param_032; 251 __u32 cfg_param_033; 252 __u32 cfg_param_034; 253 __u32 cfg_param_035; 254 __u32 cfg_param_036; 255 __u32 cfg_param_037; 256 __u32 cfg_param_038; 257 __u32 cfg_param_039; 258 __u32 cfg_param_040; 259 __u32 cfg_param_041; 260 __u32 cfg_param_042; 261 __u32 cfg_param_043; 262 __u32 cfg_param_044; 263 __u32 cfg_param_045; 264 __u32 cfg_param_046; 265 __u32 cfg_param_047; 266 __u32 cfg_param_048; 267 __u32 cfg_param_049; 268 __u32 cfg_param_050; 269 __u32 cfg_param_051; 270 __u32 cfg_param_052; 271 __u32 cfg_param_053; 272 }; 273 #define DITHER_MATRIX_SZ 16 274 struct drm_msm_dither { 275 __u64 flags; 276 __u32 temporal_en; 277 __u32 c0_bitdepth; 278 __u32 c1_bitdepth; 279 __u32 c2_bitdepth; 280 __u32 c3_bitdepth; 281 __u32 matrix[DITHER_MATRIX_SZ]; 282 }; 283 #define DRM_MSM_PA_DITHER 284 struct drm_msm_pa_dither { 285 __u64 flags; 286 __u32 strength; 287 __u32 offset_en; 288 __u32 matrix[DITHER_MATRIX_SZ]; 289 }; 290 #define DRM_MSM_AD4_ROI 291 struct drm_msm_ad4_roi_cfg { 292 __u32 h_x; 293 __u32 h_y; 294 __u32 v_x; 295 __u32 v_y; 296 __u32 factor_in; 297 __u32 factor_out; 298 }; 299 #define LTM_FEATURE_DEF 1 300 #define LTM_DATA_SIZE_0 32 301 #define LTM_DATA_SIZE_1 128 302 #define LTM_DATA_SIZE_2 256 303 #define LTM_DATA_SIZE_3 33 304 #define LTM_BUFFER_SIZE 5 305 #define LTM_GUARD_BYTES 255 306 #define LTM_BLOCK_SIZE 2 307 #define LTM_STATS_SAT (1 << 1) 308 #define LTM_STATS_MERGE_SAT (1 << 2) 309 struct drm_msm_ltm_stats_data { 310 __u32 stats_01[LTM_DATA_SIZE_0][LTM_DATA_SIZE_1]; 311 __u32 stats_02[LTM_DATA_SIZE_2]; 312 __u32 stats_03[LTM_DATA_SIZE_0]; 313 __u32 stats_04[LTM_DATA_SIZE_0]; 314 __u32 stats_05[LTM_DATA_SIZE_0]; 315 __u32 status_flag; 316 __u32 display_h; 317 __u32 display_v; 318 __u32 init_h[LTM_BLOCK_SIZE]; 319 __u32 init_v; 320 __u32 inc_h; 321 __u32 inc_v; 322 __u32 portrait_en; 323 __u32 merge_en; 324 __u32 cfg_param_01; 325 __u32 cfg_param_02; 326 __u32 cfg_param_03; 327 __u32 cfg_param_04; 328 }; 329 struct drm_msm_ltm_init_param { 330 __u32 init_param_01; 331 __u32 init_param_02; 332 __u32 init_param_03; 333 __u32 init_param_04; 334 }; 335 struct drm_msm_ltm_cfg_param { 336 __u32 cfg_param_01; 337 __u32 cfg_param_02; 338 __u32 cfg_param_03; 339 __u32 cfg_param_04; 340 __u32 cfg_param_05; 341 __u32 cfg_param_06; 342 }; 343 struct drm_msm_ltm_data { 344 __u32 data[LTM_DATA_SIZE_0][LTM_DATA_SIZE_3]; 345 }; 346 struct drm_msm_ltm_buffers_ctrl { 347 __u32 num_of_buffers; 348 __u32 fds[LTM_BUFFER_SIZE]; 349 }; 350 struct drm_msm_ltm_buffer { 351 __u32 fd; 352 __u32 offset; 353 __u32 status; 354 }; 355 #define DRM_MSM_AD4_MANUAL_STRENGTH 356 struct drm_msm_ad4_manual_str_cfg { 357 __u32 in_str; 358 __u32 out_str; 359 }; 360 #define RC_DATA_SIZE_MAX 2720 361 #define RC_CFG_SIZE_MAX 4 362 struct drm_msm_rc_mask_cfg { 363 __u64 flags; 364 __u32 cfg_param_01; 365 __u32 cfg_param_02; 366 __u32 cfg_param_03; 367 __u32 cfg_param_04[RC_CFG_SIZE_MAX]; 368 __u32 cfg_param_05[RC_CFG_SIZE_MAX]; 369 __u32 cfg_param_06[RC_CFG_SIZE_MAX]; 370 __u64 cfg_param_07; 371 __u32 cfg_param_08; 372 __u64 cfg_param_09[RC_DATA_SIZE_MAX]; 373 }; 374 #endif 375