1 #ifndef _MSM_MDP_H_ 2 #define _MSM_MDP_H_ 3 4 #include <stdint.h> 5 #include <linux/fb.h> 6 7 #define MSMFB_IOCTL_MAGIC 'm' 8 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 9 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 15 /* new ioctls's for set/get ccs matrix */ 16 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 17 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 18 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ 19 struct mdp_overlay) 20 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 21 22 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ 23 struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ 27 struct mdp_page_protection) 28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ 29 struct mdp_page_protection) 30 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ 31 struct mdp_overlay) 32 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 33 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ 34 struct msmfb_overlay_blt) 35 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 36 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ 37 struct mdp_histogram_start_req) 38 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 39 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 40 41 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ 42 struct msmfb_overlay_3d) 43 44 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ 45 struct msmfb_mixer_info_req) 46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ 47 struct msmfb_overlay_data) 48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ 52 struct msmfb_data) 53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ 54 struct msmfb_data) 55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 58 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 59 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 60 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 61 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ 62 struct mdp_display_commit) 63 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 64 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ 66 unsigned int) 67 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 68 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ 69 struct mdp_overlay_list) 70 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \ 72 struct mdp_pp_feature_version) 73 74 #define FB_TYPE_3D_PANEL 0x10101010 75 #define MDP_IMGTYPE2_START 0x10000 76 #define MSMFB_DRIVER_VERSION 0xF9E8D701 77 /* Maximum number of formats supported by MDP*/ 78 #define MDP_IMGTYPE_END 0x100 79 80 /* HW Revisions for different MDSS targets */ 81 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 82 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 83 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 84 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 85 86 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ 87 (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 88 89 #define MDSS_MDP_REV(major, minor, step) \ 90 ((((major) & 0x000F) << 28) | \ 91 (((minor) & 0x0FFF) << 16) | \ 92 ((step) & 0xFFFF)) 93 94 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ 95 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ 96 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ 97 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ 98 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ 99 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ 100 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ 101 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ 102 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */ 103 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */ 104 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */ 105 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */ 106 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */ 107 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */ 108 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */ 109 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */ 110 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ 111 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */ 112 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ 113 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ 114 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ 115 #define MDSS_MDP_HW_REV_117 MDSS_MDP_REV(1, 17, 0) /* qcs405 */ 116 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ 117 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ 118 #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ 119 #define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) /* sdm630 */ 120 121 enum { 122 NOTIFY_UPDATE_INIT, 123 NOTIFY_UPDATE_DEINIT, 124 NOTIFY_UPDATE_START, 125 NOTIFY_UPDATE_STOP, 126 NOTIFY_UPDATE_POWER_OFF, 127 }; 128 129 enum { 130 NOTIFY_TYPE_NO_UPDATE, 131 NOTIFY_TYPE_SUSPEND, 132 NOTIFY_TYPE_UPDATE, 133 NOTIFY_TYPE_BL_UPDATE, 134 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 135 }; 136 137 enum { 138 MDP_RGB_565, /* RGB 565 planer */ 139 MDP_XRGB_8888, /* RGB 888 padded */ 140 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ 141 MDP_Y_CBCR_H2V2_ADRENO, 142 MDP_ARGB_8888, /* ARGB 888 */ 143 MDP_RGB_888, /* RGB 888 planer */ 144 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ 145 MDP_YCRYCB_H2V1, /* YCrYCb interleave */ 146 MDP_CBYCRY_H2V1, /* CbYCrY interleave */ 147 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 148 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 149 MDP_Y_CRCB_H1V2, 150 MDP_Y_CBCR_H1V2, 151 MDP_RGBA_8888, /* ARGB 888 */ 152 MDP_BGRA_8888, /* ABGR 888 */ 153 MDP_RGBX_8888, /* RGBX 888 */ 154 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ 155 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ 156 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ 157 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ 158 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ 159 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ 160 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ 161 MDP_YCRCB_H1V1, /* YCrCb interleave */ 162 MDP_YCBCR_H1V1, /* YCbCr interleave */ 163 MDP_BGR_565, /* BGR 565 planer */ 164 MDP_BGR_888, /* BGR 888 */ 165 MDP_Y_CBCR_H2V2_VENUS, 166 MDP_BGRX_8888, /* BGRX 8888 */ 167 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ 168 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ 169 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ 170 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ 171 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ 172 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ 173 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ 174 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ 175 MDP_YCBYCR_H2V1, /* YCbYCr interleave */ 176 MDP_RGB_565_TILE, /* RGB 565 in tile format */ 177 MDP_BGR_565_TILE, /* BGR 565 in tile format */ 178 MDP_ARGB_1555, /*ARGB 1555*/ 179 MDP_RGBA_5551, /*RGBA 5551*/ 180 MDP_ARGB_4444, /*ARGB 4444*/ 181 MDP_RGBA_4444, /*RGBA 4444*/ 182 MDP_RGB_565_UBWC, 183 MDP_RGBA_8888_UBWC, 184 MDP_Y_CBCR_H2V2_UBWC, 185 MDP_RGBX_8888_UBWC, 186 MDP_Y_CRCB_H2V2_VENUS, 187 MDP_IMGTYPE_LIMIT, 188 MDP_RGB_BORDERFILL, /* border fill pipe */ 189 MDP_XRGB_1555, 190 MDP_RGBX_5551, 191 MDP_XRGB_4444, 192 MDP_RGBX_4444, 193 MDP_ABGR_1555, 194 MDP_BGRA_5551, 195 MDP_XBGR_1555, 196 MDP_BGRX_5551, 197 MDP_ABGR_4444, 198 MDP_BGRA_4444, 199 MDP_XBGR_4444, 200 MDP_BGRX_4444, 201 MDP_ABGR_8888, 202 MDP_XBGR_8888, 203 MDP_RGBA_1010102, 204 MDP_ARGB_2101010, 205 MDP_RGBX_1010102, 206 MDP_XRGB_2101010, 207 MDP_BGRA_1010102, 208 MDP_ABGR_2101010, 209 MDP_BGRX_1010102, 210 MDP_XBGR_2101010, 211 MDP_RGBA_1010102_UBWC, 212 MDP_RGBX_1010102_UBWC, 213 MDP_Y_CBCR_H2V2_P010, 214 MDP_Y_CBCR_H2V2_TP10_UBWC, 215 MDP_CRYCBY_H2V1, /* CrYCbY interleave */ 216 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 217 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ 218 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ 219 }; 220 221 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 222 223 enum { 224 PMEM_IMG, 225 FB_IMG, 226 }; 227 228 enum { 229 HSIC_HUE = 0, 230 HSIC_SAT, 231 HSIC_INT, 232 HSIC_CON, 233 NUM_HSIC_PARAM, 234 }; 235 236 enum mdss_mdp_max_bw_mode { 237 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 238 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 239 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 240 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 241 }; 242 243 #define MDSS_MDP_ROT_ONLY 0x80 244 #define MDSS_MDP_RIGHT_MIXER 0x100 245 #define MDSS_MDP_DUAL_PIPE 0x200 246 247 /* mdp_blit_req flag values */ 248 #define MDP_ROT_NOP 0 249 #define MDP_FLIP_LR 0x1 250 #define MDP_FLIP_UD 0x2 251 #define MDP_ROT_90 0x4 252 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) 253 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) 254 #define MDP_DITHER 0x8 255 #define MDP_BLUR 0x10 256 #define MDP_BLEND_FG_PREMULT 0x20000 257 #define MDP_IS_FG 0x40000 258 #define MDP_SOLID_FILL 0x00000020 259 #define MDP_VPU_PIPE 0x00000040 260 #define MDP_DEINTERLACE 0x80000000 261 #define MDP_SHARPENING 0x40000000 262 #define MDP_NO_DMA_BARRIER_START 0x20000000 263 #define MDP_NO_DMA_BARRIER_END 0x10000000 264 #define MDP_NO_BLIT 0x08000000 265 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 266 #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ 267 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 268 #define MDP_BLIT_SRC_GEM 0x04000000 269 #define MDP_BLIT_DST_GEM 0x02000000 270 #define MDP_BLIT_NON_CACHED 0x01000000 271 #define MDP_OV_PIPE_SHARE 0x00800000 272 #define MDP_DEINTERLACE_ODD 0x00400000 273 #define MDP_OV_PLAY_NOWAIT 0x00200000 274 #define MDP_SOURCE_ROTATED_90 0x00100000 275 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 276 #define MDP_BACKEND_COMPOSITION 0x00040000 277 #define MDP_BORDERFILL_SUPPORTED 0x00010000 278 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 279 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 280 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 281 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 282 #define MDP_BWC_EN 0x00000400 283 #define MDP_DECIMATION_EN 0x00000800 284 #define MDP_SMP_FORCE_ALLOC 0x00200000 285 #define MDP_TRANSP_NOP 0xffffffff 286 #define MDP_ALPHA_NOP 0xff 287 288 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 289 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 290 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 291 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 292 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 293 /* Sentinel: Don't use! */ 294 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 295 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ 296 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 297 298 #define MDP_DEEP_COLOR_YUV444 0x1 299 #define MDP_DEEP_COLOR_RGB30B 0x2 300 #define MDP_DEEP_COLOR_RGB36B 0x4 301 #define MDP_DEEP_COLOR_RGB48B 0x8 302 303 struct mdp_rect { 304 uint32_t x; 305 uint32_t y; 306 uint32_t w; 307 uint32_t h; 308 }; 309 310 struct mdp_img { 311 uint32_t width; 312 uint32_t height; 313 uint32_t format; 314 uint32_t offset; 315 int memory_id; /* the file descriptor */ 316 uint32_t priv; 317 }; 318 319 struct mult_factor { 320 uint32_t numer; 321 uint32_t denom; 322 }; 323 324 /* 325 * {3x3} + {3} ccs matrix 326 */ 327 328 #define MDP_CCS_RGB2YUV 0 329 #define MDP_CCS_YUV2RGB 1 330 331 #define MDP_CCS_SIZE 9 332 #define MDP_BV_SIZE 3 333 334 struct mdp_ccs { 335 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ 336 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ 337 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ 338 }; 339 340 struct mdp_csc { 341 int id; 342 uint32_t csc_mv[9]; 343 uint32_t csc_pre_bv[3]; 344 uint32_t csc_post_bv[3]; 345 uint32_t csc_pre_lv[6]; 346 uint32_t csc_post_lv[6]; 347 }; 348 349 /* The version of the mdp_blit_req structure so that 350 * user applications can selectively decide which functionality 351 * to include 352 */ 353 354 #define MDP_BLIT_REQ_VERSION 3 355 356 struct color { 357 uint32_t r; 358 uint32_t g; 359 uint32_t b; 360 uint32_t alpha; 361 }; 362 363 struct mdp_blit_req { 364 struct mdp_img src; 365 struct mdp_img dst; 366 struct mdp_rect src_rect; 367 struct mdp_rect dst_rect; 368 struct color const_color; 369 uint32_t alpha; 370 uint32_t transp_mask; 371 uint32_t flags; 372 int sharpening_strength; /* -127 <--> 127, default 64 */ 373 uint8_t color_space; 374 uint32_t fps; 375 }; 376 377 struct mdp_blit_req_list { 378 uint32_t count; 379 struct mdp_blit_req req[]; 380 }; 381 382 #define MSMFB_DATA_VERSION 2 383 384 struct msmfb_data { 385 uint32_t offset; 386 int memory_id; 387 int id; 388 uint32_t flags; 389 uint32_t priv; 390 uint32_t iova; 391 }; 392 393 #define MSMFB_NEW_REQUEST -1 394 395 struct msmfb_overlay_data { 396 uint32_t id; 397 struct msmfb_data data; 398 uint32_t version_key; 399 struct msmfb_data plane1_data; 400 struct msmfb_data plane2_data; 401 struct msmfb_data dst_data; 402 }; 403 404 struct msmfb_img { 405 uint32_t width; 406 uint32_t height; 407 uint32_t format; 408 }; 409 410 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 411 struct msmfb_writeback_data { 412 struct msmfb_data buf_info; 413 struct msmfb_img img; 414 }; 415 416 #define MDP_PP_OPS_ENABLE 0x1 417 #define MDP_PP_OPS_READ 0x2 418 #define MDP_PP_OPS_WRITE 0x4 419 #define MDP_PP_OPS_DISABLE 0x8 420 #define MDP_PP_IGC_FLAG_ROM0 0x10 421 #define MDP_PP_IGC_FLAG_ROM1 0x20 422 423 424 #define MDSS_PP_DSPP_CFG 0x000 425 #define MDSS_PP_SSPP_CFG 0x100 426 #define MDSS_PP_LM_CFG 0x200 427 #define MDSS_PP_WB_CFG 0x300 428 429 #define MDSS_PP_ARG_MASK 0x3C00 430 #define MDSS_PP_ARG_NUM 4 431 #define MDSS_PP_ARG_SHIFT 10 432 #define MDSS_PP_LOCATION_MASK 0x0300 433 #define MDSS_PP_LOGICAL_MASK 0x00FF 434 435 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 436 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 437 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 438 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 439 440 441 struct mdp_qseed_cfg { 442 uint32_t table_num; 443 uint32_t ops; 444 uint32_t len; 445 uint32_t *data; 446 }; 447 448 struct mdp_sharp_cfg { 449 uint32_t flags; 450 uint32_t strength; 451 uint32_t edge_thr; 452 uint32_t smooth_thr; 453 uint32_t noise_thr; 454 }; 455 456 struct mdp_qseed_cfg_data { 457 uint32_t block; 458 struct mdp_qseed_cfg qseed_data; 459 }; 460 461 #define MDP_OVERLAY_PP_CSC_CFG 0x1 462 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 463 #define MDP_OVERLAY_PP_PA_CFG 0x4 464 #define MDP_OVERLAY_PP_IGC_CFG 0x8 465 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 466 #define MDP_OVERLAY_PP_HIST_CFG 0x20 467 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 468 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 469 #define MDP_OVERLAY_PP_PCC_CFG 0x100 470 471 #define MDP_CSC_FLAG_ENABLE 0x1 472 #define MDP_CSC_FLAG_YUV_IN 0x2 473 #define MDP_CSC_FLAG_YUV_OUT 0x4 474 475 #define MDP_CSC_MATRIX_COEFF_SIZE 9 476 #define MDP_CSC_CLAMP_SIZE 6 477 #define MDP_CSC_BIAS_SIZE 3 478 479 struct mdp_csc_cfg { 480 /* flags for enable CSC, toggling RGB,YUV input/output */ 481 uint32_t flags; 482 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 483 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 484 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 485 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 486 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 487 }; 488 489 struct mdp_csc_cfg_data { 490 uint32_t block; 491 struct mdp_csc_cfg csc_data; 492 }; 493 494 struct mdp_pa_cfg { 495 uint32_t flags; 496 uint32_t hue_adj; 497 uint32_t sat_adj; 498 uint32_t val_adj; 499 uint32_t cont_adj; 500 }; 501 502 struct mdp_pa_mem_col_cfg { 503 uint32_t color_adjust_p0; 504 uint32_t color_adjust_p1; 505 uint32_t hue_region; 506 uint32_t sat_region; 507 uint32_t val_region; 508 }; 509 510 #define MDP_SIX_ZONE_LUT_SIZE 384 511 512 /* PA Write/Read extension flags */ 513 #define MDP_PP_PA_HUE_ENABLE 0x10 514 #define MDP_PP_PA_SAT_ENABLE 0x20 515 #define MDP_PP_PA_VAL_ENABLE 0x40 516 #define MDP_PP_PA_CONT_ENABLE 0x80 517 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 518 #define MDP_PP_PA_SKIN_ENABLE 0x200 519 #define MDP_PP_PA_SKY_ENABLE 0x400 520 #define MDP_PP_PA_FOL_ENABLE 0x800 521 522 /* PA masks */ 523 /* Masks used in PA v1_7 only */ 524 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 525 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 526 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 527 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 528 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 529 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 530 /* Masks used in all PAv2 versions */ 531 #define MDP_PP_PA_HUE_MASK 0x1000 532 #define MDP_PP_PA_SAT_MASK 0x2000 533 #define MDP_PP_PA_VAL_MASK 0x4000 534 #define MDP_PP_PA_CONT_MASK 0x8000 535 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 536 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 537 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 538 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 539 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 540 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 541 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 542 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 543 544 /* Flags for setting PA saturation and value hold */ 545 #define MDP_PP_PA_LEFT_HOLD 0x1 546 #define MDP_PP_PA_RIGHT_HOLD 0x2 547 548 struct mdp_pa_v2_data { 549 /* Mask bits for PA features */ 550 uint32_t flags; 551 uint32_t global_hue_adj; 552 uint32_t global_sat_adj; 553 uint32_t global_val_adj; 554 uint32_t global_cont_adj; 555 struct mdp_pa_mem_col_cfg skin_cfg; 556 struct mdp_pa_mem_col_cfg sky_cfg; 557 struct mdp_pa_mem_col_cfg fol_cfg; 558 uint32_t six_zone_len; 559 uint32_t six_zone_thresh; 560 uint32_t *six_zone_curve_p0; 561 uint32_t *six_zone_curve_p1; 562 }; 563 564 struct mdp_pa_mem_col_data_v1_7 { 565 uint32_t color_adjust_p0; 566 uint32_t color_adjust_p1; 567 uint32_t color_adjust_p2; 568 uint32_t blend_gain; 569 uint8_t sat_hold; 570 uint8_t val_hold; 571 uint32_t hue_region; 572 uint32_t sat_region; 573 uint32_t val_region; 574 }; 575 576 struct mdp_pa_data_v1_7 { 577 uint32_t mode; 578 uint32_t global_hue_adj; 579 uint32_t global_sat_adj; 580 uint32_t global_val_adj; 581 uint32_t global_cont_adj; 582 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 583 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 584 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 585 uint32_t six_zone_thresh; 586 uint32_t six_zone_adj_p0; 587 uint32_t six_zone_adj_p1; 588 uint8_t six_zone_sat_hold; 589 uint8_t six_zone_val_hold; 590 uint32_t six_zone_len; 591 uint32_t *six_zone_curve_p0; 592 uint32_t *six_zone_curve_p1; 593 }; 594 595 596 struct mdp_pa_v2_cfg_data { 597 uint32_t version; 598 uint32_t block; 599 uint32_t flags; 600 struct mdp_pa_v2_data pa_v2_data; 601 void *cfg_payload; 602 }; 603 604 605 enum { 606 mdp_igc_rec601 = 1, 607 mdp_igc_rec709, 608 mdp_igc_srgb, 609 mdp_igc_custom, 610 mdp_igc_rec_max, 611 }; 612 613 struct mdp_igc_lut_data { 614 uint32_t block; 615 uint32_t version; 616 uint32_t len, ops; 617 uint32_t *c0_c1_data; 618 uint32_t *c2_data; 619 void *cfg_payload; 620 }; 621 622 struct mdp_igc_lut_data_v1_7 { 623 uint32_t table_fmt; 624 uint32_t len; 625 uint32_t *c0_c1_data; 626 uint32_t *c2_data; 627 }; 628 629 struct mdp_igc_lut_data_payload { 630 uint32_t table_fmt; 631 uint32_t len; 632 uint64_t c0_c1_data; 633 uint64_t c2_data; 634 uint32_t strength; 635 }; 636 637 struct mdp_histogram_cfg { 638 uint32_t ops; 639 uint32_t block; 640 uint8_t frame_cnt; 641 uint8_t bit_mask; 642 uint16_t num_bins; 643 }; 644 645 struct mdp_hist_lut_data_v1_7 { 646 uint32_t len; 647 uint32_t *data; 648 }; 649 650 struct mdp_hist_lut_data { 651 uint32_t block; 652 uint32_t version; 653 uint32_t hist_lut_first; 654 uint32_t ops; 655 uint32_t len; 656 uint32_t *data; 657 void *cfg_payload; 658 }; 659 660 struct mdp_pcc_coeff { 661 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 662 }; 663 664 struct mdp_pcc_coeff_v1_7 { 665 uint32_t c, r, g, b, rg, gb, rb, rgb; 666 }; 667 668 struct mdp_pcc_data_v1_7 { 669 struct mdp_pcc_coeff_v1_7 r, g, b; 670 }; 671 672 struct mdp_pcc_cfg_data { 673 uint32_t version; 674 uint32_t block; 675 uint32_t ops; 676 struct mdp_pcc_coeff r, g, b; 677 void *cfg_payload; 678 }; 679 680 enum { 681 mdp_lut_igc, 682 mdp_lut_pgc, 683 mdp_lut_hist, 684 mdp_lut_rgb, 685 mdp_lut_max, 686 }; 687 struct mdp_overlay_pp_params { 688 uint32_t config_ops; 689 struct mdp_csc_cfg csc_cfg; 690 struct mdp_qseed_cfg qseed_cfg[2]; 691 struct mdp_pa_cfg pa_cfg; 692 struct mdp_pa_v2_data pa_v2_cfg; 693 struct mdp_igc_lut_data igc_cfg; 694 struct mdp_sharp_cfg sharp_cfg; 695 struct mdp_histogram_cfg hist_cfg; 696 struct mdp_hist_lut_data hist_lut_cfg; 697 /* PAv2 cfg data for PA 2.x versions */ 698 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 699 struct mdp_pcc_cfg_data pcc_cfg_data; 700 }; 701 702 /** 703 * enum mdss_mdp_blend_op - Different blend operations set by userspace 704 * 705 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 706 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 707 * would appear opaque in case fg plane alpha is 708 * 0xff. 709 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has 710 * alpha pre-multiplication done. If fg plane alpha 711 * is less than 0xff, apply modulation as well. This 712 * operation is intended on layers having alpha 713 * channel. 714 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha 715 * pre-multiplied. Apply pre-multiplication. If fg 716 * plane alpha is less than 0xff, apply modulation as 717 * well. 718 * @BLEND_OP_MAX: Used to track maximum blend operation possible by 719 * mdp. 720 */ 721 enum mdss_mdp_blend_op { 722 BLEND_OP_NOT_DEFINED = 0, 723 BLEND_OP_OPAQUE, 724 BLEND_OP_PREMULTIPLIED, 725 BLEND_OP_COVERAGE, 726 BLEND_OP_MAX, 727 }; 728 729 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 730 #define MAX_PLANES 4 731 struct mdp_scale_data { 732 uint8_t enable_pxl_ext; 733 734 int init_phase_x[MAX_PLANES]; 735 int phase_step_x[MAX_PLANES]; 736 int init_phase_y[MAX_PLANES]; 737 int phase_step_y[MAX_PLANES]; 738 739 int num_ext_pxls_left[MAX_PLANES]; 740 int num_ext_pxls_right[MAX_PLANES]; 741 int num_ext_pxls_top[MAX_PLANES]; 742 int num_ext_pxls_btm[MAX_PLANES]; 743 744 int left_ftch[MAX_PLANES]; 745 int left_rpt[MAX_PLANES]; 746 int right_ftch[MAX_PLANES]; 747 int right_rpt[MAX_PLANES]; 748 749 int top_rpt[MAX_PLANES]; 750 int btm_rpt[MAX_PLANES]; 751 int top_ftch[MAX_PLANES]; 752 int btm_ftch[MAX_PLANES]; 753 754 uint32_t roi_w[MAX_PLANES]; 755 }; 756 757 /** 758 * enum mdp_overlay_pipe_type - Different pipe type set by userspace 759 * 760 * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. 761 * @PIPE_TYPE_VIG: VIG pipe. 762 * @PIPE_TYPE_RGB: RGB pipe. 763 * @PIPE_TYPE_DMA: DMA pipe. 764 * @PIPE_TYPE_CURSOR: CURSOR pipe. 765 * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. 766 */ 767 enum mdp_overlay_pipe_type { 768 PIPE_TYPE_AUTO = 0, 769 PIPE_TYPE_VIG, 770 PIPE_TYPE_RGB, 771 PIPE_TYPE_DMA, 772 PIPE_TYPE_CURSOR, 773 PIPE_TYPE_MAX, 774 }; 775 776 /** 777 * struct mdp_overlay - overlay surface structure 778 * @src: Source image information (width, height, format). 779 * @src_rect: Source crop rectangle, portion of image that will be fetched. 780 * This should always be within boundaries of source image. 781 * @dst_rect: Destination rectangle, the position and size of image on screen. 782 * This should always be within panel boundaries. 783 * @z_order: Blending stage to occupy in display, if multiple layers are 784 * present, highest z_order usually means the top most visible 785 * layer. The range acceptable is from 0-3 to support blending 786 * up to 4 layers. 787 * @is_fg: This flag is used to disable blending of any layers with z_order 788 * less than this overlay. It means that any layers with z_order 789 * less than this layer will not be blended and will be replaced 790 * by the background border color. 791 * @alpha: Used to set plane opacity. The range can be from 0-255, where 792 * 0 means completely transparent and 255 means fully opaque. 793 * @transp_mask: Color used as color key for transparency. Any pixel in fetched 794 * image matching this color will be transparent when blending. 795 * The color should be in same format as the source image format. 796 * @flags: This is used to customize operation of overlay. See MDP flags 797 * for more information. 798 * @pipe_type: Used to specify the type of overlay pipe. 799 * @user_data: DEPRECATED* Used to store user application specific information. 800 * @bg_color: Solid color used to fill the overlay surface when no source 801 * buffer is provided. 802 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels 803 * dropped for each pixel that is fetched from a line. The value 804 * given should be power of two of decimation amount. 805 * 0: no decimation 806 * 1: decimate by 2 (drop 1 pixel for each pixel fetched) 807 * 2: decimate by 4 (drop 3 pixels for each pixel fetched) 808 * 3: decimate by 8 (drop 7 pixels for each pixel fetched) 809 * 4: decimate by 16 (drop 15 pixels for each pixel fetched) 810 * @vert_deci: Vertical decimation value, this indicates the amount of lines 811 * dropped for each line that is fetched from overlay. The value 812 * given should be power of two of decimation amount. 813 * 0: no decimation 814 * 1: decimation by 2 (drop 1 line for each line fetched) 815 * 2: decimation by 4 (drop 3 lines for each line fetched) 816 * 3: decimation by 8 (drop 7 lines for each line fetched) 817 * 4: decimation by 16 (drop 15 lines for each line fetched) 818 * @overlay_pp_cfg: Overlay post processing configuration, for more information 819 * see struct mdp_overlay_pp_params. 820 * @priority: Priority is returned by the driver when overlay is set for the 821 * first time. It indicates the priority of the underlying pipe 822 * serving the overlay. This priority can be used by user-space 823 * in source split when pipes are re-used and shuffled around to 824 * reduce fallbacks. 825 */ 826 struct mdp_overlay { 827 struct msmfb_img src; 828 struct mdp_rect src_rect; 829 struct mdp_rect dst_rect; 830 uint32_t z_order; /* stage number */ 831 uint32_t is_fg; /* control alpha & transp */ 832 uint32_t alpha; 833 uint32_t blend_op; 834 uint32_t transp_mask; 835 uint32_t flags; 836 uint32_t pipe_type; 837 uint32_t id; 838 uint8_t priority; 839 uint32_t user_data[6]; 840 uint32_t bg_color; 841 uint8_t horz_deci; 842 uint8_t vert_deci; 843 struct mdp_overlay_pp_params overlay_pp_cfg; 844 struct mdp_scale_data scale; 845 uint8_t color_space; 846 uint32_t frame_rate; 847 }; 848 849 struct msmfb_overlay_3d { 850 uint32_t is_3d; 851 uint32_t width; 852 uint32_t height; 853 }; 854 855 856 struct msmfb_overlay_blt { 857 uint32_t enable; 858 uint32_t offset; 859 uint32_t width; 860 uint32_t height; 861 uint32_t bpp; 862 }; 863 864 struct mdp_histogram { 865 uint32_t frame_cnt; 866 uint32_t bin_cnt; 867 uint32_t *r; 868 uint32_t *g; 869 uint32_t *b; 870 }; 871 872 #define MISR_CRC_BATCH_SIZE 32 873 enum { 874 DISPLAY_MISR_EDP, 875 DISPLAY_MISR_DSI0, 876 DISPLAY_MISR_DSI1, 877 DISPLAY_MISR_HDMI, 878 DISPLAY_MISR_LCDC, 879 DISPLAY_MISR_MDP, 880 DISPLAY_MISR_ATV, 881 DISPLAY_MISR_DSI_CMD, 882 DISPLAY_MISR_MAX 883 }; 884 885 enum { 886 MISR_OP_NONE, 887 MISR_OP_SFM, 888 MISR_OP_MFM, 889 MISR_OP_BM, 890 MISR_OP_MAX 891 }; 892 893 struct mdp_misr { 894 uint32_t block_id; 895 uint32_t frame_count; 896 uint32_t crc_op_mode; 897 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 898 }; 899 900 /* 901 * mdp_block_type defines the identifiers for pipes in MDP 4.3 and up 902 * 903 * MDP_BLOCK_RESERVED is provided for backward compatibility and is 904 * deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used 905 * instead. 906 * 907 * MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, 908 * same for others. 909 */ 910 911 enum { 912 MDP_BLOCK_RESERVED = 0, 913 MDP_BLOCK_OVERLAY_0, 914 MDP_BLOCK_OVERLAY_1, 915 MDP_BLOCK_VG_1, 916 MDP_BLOCK_VG_2, 917 MDP_BLOCK_RGB_1, 918 MDP_BLOCK_RGB_2, 919 MDP_BLOCK_DMA_P, 920 MDP_BLOCK_DMA_S, 921 MDP_BLOCK_DMA_E, 922 MDP_BLOCK_OVERLAY_2, 923 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 924 MDP_LOGICAL_BLOCK_DISP_1, 925 MDP_LOGICAL_BLOCK_DISP_2, 926 MDP_BLOCK_MAX, 927 }; 928 929 /* 930 * mdp_histogram_start_req is used to provide the parameters for 931 * histogram start request 932 */ 933 934 struct mdp_histogram_start_req { 935 uint32_t block; 936 uint8_t frame_cnt; 937 uint8_t bit_mask; 938 uint16_t num_bins; 939 }; 940 941 /* 942 * mdp_histogram_data is used to return the histogram data, once 943 * the histogram is done/stopped/cance 944 */ 945 946 struct mdp_histogram_data { 947 uint32_t block; 948 uint32_t bin_cnt; 949 uint32_t *c0; 950 uint32_t *c1; 951 uint32_t *c2; 952 uint32_t *extra_info; 953 }; 954 955 956 #define GC_LUT_ENTRIES_V1_7 512 957 958 struct mdp_ar_gc_lut_data { 959 uint32_t x_start; 960 uint32_t slope; 961 uint32_t offset; 962 }; 963 964 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 965 struct mdp_pgc_lut_data { 966 uint32_t version; 967 uint32_t block; 968 uint32_t flags; 969 uint8_t num_r_stages; 970 uint8_t num_g_stages; 971 uint8_t num_b_stages; 972 struct mdp_ar_gc_lut_data *r_data; 973 struct mdp_ar_gc_lut_data *g_data; 974 struct mdp_ar_gc_lut_data *b_data; 975 void *cfg_payload; 976 }; 977 978 #define PGC_LUT_ENTRIES 1024 979 struct mdp_pgc_lut_data_v1_7 { 980 uint32_t len; 981 uint32_t *c0_data; 982 uint32_t *c1_data; 983 uint32_t *c2_data; 984 }; 985 986 /* 987 * mdp_rgb_lut_data is used to provide parameters for configuring the 988 * generic RGB lut in case of gamma correction or other LUT updation usecases 989 */ 990 struct mdp_rgb_lut_data { 991 uint32_t flags; 992 uint32_t lut_type; 993 struct fb_cmap cmap; 994 }; 995 996 enum { 997 mdp_rgb_lut_gc, 998 mdp_rgb_lut_hist, 999 }; 1000 1001 struct mdp_lut_cfg_data { 1002 uint32_t lut_type; 1003 union { 1004 struct mdp_igc_lut_data igc_lut_data; 1005 struct mdp_pgc_lut_data pgc_lut_data; 1006 struct mdp_hist_lut_data hist_lut_data; 1007 struct mdp_rgb_lut_data rgb_lut_data; 1008 } data; 1009 }; 1010 1011 struct mdp_bl_scale_data { 1012 uint32_t min_lvl; 1013 uint32_t scale; 1014 }; 1015 1016 struct mdp_pa_cfg_data { 1017 uint32_t block; 1018 struct mdp_pa_cfg pa_data; 1019 }; 1020 1021 #define MDP_DITHER_DATA_V1_7_SZ 16 1022 1023 struct mdp_dither_data_v1_7 { 1024 uint32_t g_y_depth; 1025 uint32_t r_cr_depth; 1026 uint32_t b_cb_depth; 1027 uint32_t len; 1028 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 1029 uint32_t temporal_en; 1030 }; 1031 1032 struct mdp_pa_dither_data { 1033 uint64_t data_flags; 1034 uint32_t matrix_sz; 1035 uint64_t matrix_data; 1036 uint32_t strength; 1037 uint32_t offset_en; 1038 }; 1039 1040 struct mdp_dither_cfg_data { 1041 uint32_t version; 1042 uint32_t block; 1043 uint32_t flags; 1044 uint32_t mode; 1045 uint32_t g_y_depth; 1046 uint32_t r_cr_depth; 1047 uint32_t b_cb_depth; 1048 void *cfg_payload; 1049 }; 1050 1051 #define MDP_GAMUT_TABLE_NUM 8 1052 #define MDP_GAMUT_TABLE_NUM_V1_7 4 1053 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 1054 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 1055 #define MDP_GAMUT_SCALE_OFF_SZ 16 1056 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 1057 1058 struct mdp_gamut_cfg_data { 1059 uint32_t block; 1060 uint32_t flags; 1061 uint32_t version; 1062 /* v1 version specific params */ 1063 uint32_t gamut_first; 1064 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 1065 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; 1066 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; 1067 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; 1068 /* params for newer versions of gamut */ 1069 void *cfg_payload; 1070 }; 1071 1072 enum { 1073 mdp_gamut_fine_mode = 0x1, 1074 mdp_gamut_coarse_mode, 1075 }; 1076 1077 struct mdp_gamut_data_v1_7 { 1078 uint32_t mode; 1079 uint32_t map_en; 1080 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 1081 uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1082 uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 1083 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1084 uint32_t *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 1085 }; 1086 1087 struct mdp_calib_config_data { 1088 uint32_t ops; 1089 uint32_t addr; 1090 uint32_t data; 1091 }; 1092 1093 struct mdp_calib_config_buffer { 1094 uint32_t ops; 1095 uint32_t size; 1096 uint32_t *buffer; 1097 }; 1098 1099 struct mdp_calib_dcm_state { 1100 uint32_t ops; 1101 uint32_t dcm_state; 1102 }; 1103 1104 enum { 1105 DCM_UNINIT, 1106 DCM_UNBLANK, 1107 DCM_ENTER, 1108 DCM_EXIT, 1109 DCM_BLANK, 1110 DTM_ENTER, 1111 DTM_EXIT, 1112 }; 1113 1114 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 1115 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 1116 #define MDSS_PP_SPLIT_MASK 0x30000000 1117 1118 #define MDSS_MAX_BL_BRIGHTNESS 255 1119 #define AD_BL_LIN_LEN 256 1120 #define AD_BL_ATT_LUT_LEN 33 1121 1122 #define MDSS_AD_MODE_AUTO_BL 0x0 1123 #define MDSS_AD_MODE_AUTO_STR 0x1 1124 #define MDSS_AD_MODE_TARG_STR 0x3 1125 #define MDSS_AD_MODE_MAN_STR 0x7 1126 #define MDSS_AD_MODE_CALIB 0xF 1127 1128 #define MDP_PP_AD_INIT 0x10 1129 #define MDP_PP_AD_CFG 0x20 1130 1131 struct mdss_ad_init { 1132 uint32_t asym_lut[33]; 1133 uint32_t color_corr_lut[33]; 1134 uint8_t i_control[2]; 1135 uint16_t black_lvl; 1136 uint16_t white_lvl; 1137 uint8_t var; 1138 uint8_t limit_ampl; 1139 uint8_t i_dither; 1140 uint8_t slope_max; 1141 uint8_t slope_min; 1142 uint8_t dither_ctl; 1143 uint8_t format; 1144 uint8_t auto_size; 1145 uint16_t frame_w; 1146 uint16_t frame_h; 1147 uint8_t logo_v; 1148 uint8_t logo_h; 1149 uint32_t alpha; 1150 uint32_t alpha_base; 1151 uint32_t al_thresh; 1152 uint32_t bl_lin_len; 1153 uint32_t bl_att_len; 1154 uint32_t *bl_lin; 1155 uint32_t *bl_lin_inv; 1156 uint32_t *bl_att_lut; 1157 }; 1158 1159 #define MDSS_AD_BL_CTRL_MODE_EN 1 1160 #define MDSS_AD_BL_CTRL_MODE_DIS 0 1161 struct mdss_ad_cfg { 1162 uint32_t mode; 1163 uint32_t al_calib_lut[33]; 1164 uint16_t backlight_min; 1165 uint16_t backlight_max; 1166 uint16_t backlight_scale; 1167 uint16_t amb_light_min; 1168 uint16_t filter[2]; 1169 uint16_t calib[4]; 1170 uint8_t strength_limit; 1171 uint8_t t_filter_recursion; 1172 uint16_t stab_itr; 1173 uint32_t bl_ctrl_mode; 1174 }; 1175 1176 struct mdss_ad_bl_cfg { 1177 uint32_t bl_min_delta; 1178 uint32_t bl_low_limit; 1179 }; 1180 1181 /* ops uses standard MDP_PP_* flags */ 1182 struct mdss_ad_init_cfg { 1183 uint32_t ops; 1184 union { 1185 struct mdss_ad_init init; 1186 struct mdss_ad_cfg cfg; 1187 } params; 1188 }; 1189 1190 /* mode uses MDSS_AD_MODE_* flags */ 1191 struct mdss_ad_input { 1192 uint32_t mode; 1193 union { 1194 uint32_t amb_light; 1195 uint32_t strength; 1196 uint32_t calib_bl; 1197 } in; 1198 uint32_t output; 1199 }; 1200 1201 #define MDSS_CALIB_MODE_BL 0x1 1202 struct mdss_calib_cfg { 1203 uint32_t ops; 1204 uint32_t calib_mask; 1205 }; 1206 1207 enum { 1208 mdp_op_pcc_cfg, 1209 mdp_op_csc_cfg, 1210 mdp_op_lut_cfg, 1211 mdp_op_qseed_cfg, 1212 mdp_bl_scale_cfg, 1213 mdp_op_pa_cfg, 1214 mdp_op_pa_v2_cfg, 1215 mdp_op_dither_cfg, 1216 mdp_op_gamut_cfg, 1217 mdp_op_calib_cfg, 1218 mdp_op_ad_cfg, 1219 mdp_op_ad_input, 1220 mdp_op_calib_mode, 1221 mdp_op_calib_buffer, 1222 mdp_op_calib_dcm_state, 1223 mdp_op_max, 1224 mdp_op_pa_dither_cfg, 1225 mdp_op_ad_bl_cfg, 1226 mdp_op_pp_max = 255, 1227 }; 1228 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 1229 #define mdp_op_pp_max mdp_op_pp_max 1230 1231 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 1232 1233 enum { 1234 WB_FORMAT_NV12, 1235 WB_FORMAT_RGB_565, 1236 WB_FORMAT_RGB_888, 1237 WB_FORMAT_xRGB_8888, 1238 WB_FORMAT_ARGB_8888, 1239 WB_FORMAT_BGRA_8888, 1240 WB_FORMAT_BGRX_8888, 1241 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ 1242 }; 1243 1244 struct msmfb_mdp_pp { 1245 uint32_t op; 1246 union { 1247 struct mdp_pcc_cfg_data pcc_cfg_data; 1248 struct mdp_csc_cfg_data csc_cfg_data; 1249 struct mdp_lut_cfg_data lut_cfg_data; 1250 struct mdp_qseed_cfg_data qseed_cfg_data; 1251 struct mdp_bl_scale_data bl_scale_data; 1252 struct mdp_pa_cfg_data pa_cfg_data; 1253 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 1254 struct mdp_dither_cfg_data dither_cfg_data; 1255 struct mdp_gamut_cfg_data gamut_cfg_data; 1256 struct mdp_calib_config_data calib_cfg; 1257 struct mdss_ad_init_cfg ad_init_cfg; 1258 struct mdss_calib_cfg mdss_calib_cfg; 1259 struct mdss_ad_input ad_input; 1260 struct mdp_calib_config_buffer calib_buffer; 1261 struct mdp_calib_dcm_state calib_dcm; 1262 struct mdss_ad_bl_cfg ad_bl_cfg; 1263 } data; 1264 }; 1265 1266 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1267 enum { 1268 metadata_op_none, 1269 metadata_op_base_blend, 1270 metadata_op_frame_rate, 1271 metadata_op_vic, 1272 metadata_op_wb_format, 1273 metadata_op_wb_secure, 1274 metadata_op_get_caps, 1275 metadata_op_crc, 1276 metadata_op_get_ion_fd, 1277 metadata_op_max 1278 }; 1279 1280 struct mdp_blend_cfg { 1281 uint32_t is_premultiplied; 1282 }; 1283 1284 struct mdp_mixer_cfg { 1285 uint32_t writeback_format; 1286 uint32_t alpha; 1287 }; 1288 1289 struct mdss_hw_caps { 1290 uint32_t mdp_rev; 1291 uint8_t rgb_pipes; 1292 uint8_t vig_pipes; 1293 uint8_t dma_pipes; 1294 uint8_t max_smp_cnt; 1295 uint8_t smp_per_pipe; 1296 uint32_t features; 1297 }; 1298 1299 struct msmfb_metadata { 1300 uint32_t op; 1301 uint32_t flags; 1302 union { 1303 struct mdp_misr misr_request; 1304 struct mdp_blend_cfg blend_cfg; 1305 struct mdp_mixer_cfg mixer_cfg; 1306 uint32_t panel_frame_rate; 1307 uint32_t video_info_code; 1308 struct mdss_hw_caps caps; 1309 uint8_t secure_en; 1310 int fbmem_ionfd; 1311 } data; 1312 }; 1313 1314 #define MDP_MAX_FENCE_FD 32 1315 #define MDP_BUF_SYNC_FLAG_WAIT 1 1316 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1317 1318 struct mdp_buf_sync { 1319 uint32_t flags; 1320 uint32_t acq_fen_fd_cnt; 1321 uint32_t session_id; 1322 int *acq_fen_fd; 1323 int *rel_fen_fd; 1324 int *retire_fen_fd; 1325 }; 1326 1327 struct mdp_async_blit_req_list { 1328 struct mdp_buf_sync sync; 1329 uint32_t count; 1330 struct mdp_blit_req req[]; 1331 }; 1332 1333 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1334 1335 struct mdp_display_commit { 1336 uint32_t flags; 1337 uint32_t wait_for_finish; 1338 struct fb_var_screeninfo var; 1339 /* 1340 * user needs to follow guidelines as per below rules 1341 * 1. source split is enabled: l_roi = roi and r_roi = 0 1342 * 2. source split is disabled: 1343 * 2.1 split display: l_roi = l_roi and r_roi = r_roi 1344 * 2.2 non split display: l_roi = roi and r_roi = 0 1345 */ 1346 struct mdp_rect l_roi; 1347 struct mdp_rect r_roi; 1348 }; 1349 1350 /** 1351 * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE 1352 * @num_overlays: Number of overlay layers as part of the frame. 1353 * @overlay_list: Pointer to a list of overlay structures identifying 1354 * the layers as part of the frame 1355 * @flags: Flags can be used to extend behavior. 1356 * @processed_overlays: Output parameter indicating how many pipes were 1357 * successful. If there are no errors this number should 1358 * match num_overlays. Otherwise it will indicate the last 1359 * successful index for overlay that couldn't be set. 1360 */ 1361 struct mdp_overlay_list { 1362 uint32_t num_overlays; 1363 struct mdp_overlay **overlay_list; 1364 uint32_t flags; 1365 uint32_t processed_overlays; 1366 }; 1367 1368 struct mdp_page_protection { 1369 uint32_t page_protection; 1370 }; 1371 1372 1373 struct mdp_mixer_info { 1374 int pndx; 1375 int pnum; 1376 int ptype; 1377 int mixer_num; 1378 int z_order; 1379 }; 1380 1381 #define MAX_PIPE_PER_MIXER 7 1382 1383 struct msmfb_mixer_info_req { 1384 int mixer_num; 1385 int cnt; 1386 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1387 }; 1388 1389 enum { 1390 DISPLAY_SUBSYSTEM_ID, 1391 ROTATOR_SUBSYSTEM_ID, 1392 }; 1393 1394 enum { 1395 MDP_IOMMU_DOMAIN_CP, 1396 MDP_IOMMU_DOMAIN_NS, 1397 }; 1398 1399 enum { 1400 MDP_WRITEBACK_MIRROR_OFF, 1401 MDP_WRITEBACK_MIRROR_ON, 1402 MDP_WRITEBACK_MIRROR_PAUSE, 1403 MDP_WRITEBACK_MIRROR_RESUME, 1404 }; 1405 1406 enum mdp_color_space { 1407 MDP_CSC_ITU_R_601, 1408 MDP_CSC_ITU_R_601_FR, 1409 MDP_CSC_ITU_R_709, 1410 }; 1411 1412 /* 1413 * These definitions are a continuation of the mdp_color_space enum above 1414 */ 1415 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1416 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1417 enum { 1418 mdp_igc_v1_7 = 1, 1419 mdp_igc_vmax, 1420 mdp_hist_lut_v1_7, 1421 mdp_hist_lut_vmax, 1422 mdp_pgc_v1_7, 1423 mdp_pgc_vmax, 1424 mdp_dither_v1_7, 1425 mdp_dither_vmax, 1426 mdp_gamut_v1_7, 1427 mdp_gamut_vmax, 1428 mdp_pa_v1_7, 1429 mdp_pa_vmax, 1430 mdp_pcc_v1_7, 1431 mdp_pcc_vmax, 1432 mdp_pp_legacy, 1433 mdp_dither_pa_v1_7, 1434 mdp_igc_v3, 1435 mdp_pp_unknown = 255 1436 }; 1437 1438 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1439 #define mdp_pp_unknown mdp_pp_unknown 1440 #define mdp_igc_v3 mdp_igc_v3 1441 1442 /* PP Features */ 1443 enum { 1444 IGC = 1, 1445 PCC, 1446 GC, 1447 PA, 1448 GAMUT, 1449 DITHER, 1450 QSEED, 1451 HIST_LUT, 1452 HIST, 1453 PP_FEATURE_MAX, 1454 PA_DITHER, 1455 PP_MAX_FEATURES = 25, 1456 }; 1457 1458 #define PA_DITHER PA_DITHER 1459 #define PP_MAX_FEATURES PP_MAX_FEATURES 1460 1461 struct mdp_pp_feature_version { 1462 uint32_t pp_feature; 1463 uint32_t version_info; 1464 }; 1465 #endif /* _MSM_MDP_H_*/ 1466