1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27 #include "drm.h"
28
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32
33 /**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and
63 * applications.
64 *
65 * The authoritative list of format modifier codes is found in
66 * `include/uapi/drm/drm_fourcc.h`
67 */
68
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
70 ((__u32)(c) << 16) | ((__u32)(d) << 24))
71
72 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
73
74 /* Reserve 0 for the invalid format specifier */
75 #define DRM_FORMAT_INVALID 0
76
77 /* color index */
78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
79
80 /* 8 bpp Red */
81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
82
83 /* 16 bpp Red */
84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
85
86 /* 16 bpp RG */
87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
89
90 /* 32 bpp RG */
91 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
92 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
93
94 /* 8 bpp RGB */
95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
97
98 /* 16 bpp RGB */
99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
103
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
108
109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
113
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
118
119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
121
122 /* 24 bpp RGB */
123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
125
126 /* 32 bpp RGB */
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
131
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
136
137 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
138 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
139 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
140 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
141
142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
146
147 /*
148 * Floating point 64bpp RGB
149 * IEEE 754-2008 binary16 half-precision float
150 * [15:0] sign:exponent:mantissa 1:5:10
151 */
152 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
153 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
154
155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
157
158 /* packed YCbCr */
159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
163
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
167 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
168
169 /*
170 * packed Y2xx indicate for each component, xx valid data occupy msb
171 * 16-xx padding occupy lsb
172 */
173 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
174 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
175 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
176
177 /*
178 * packed Y4xx indicate for each component, xx valid data occupy msb
179 * 16-xx padding occupy lsb except Y410
180 */
181 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
182 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
183 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
184
185 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
186 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
187 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
188
189 /*
190 * packed YCbCr420 2x2 tiled formats
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
192 */
193 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
194 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
195 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
196 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
197
198 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
199 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
200 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
201 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
202
203 /*
204 * 1-plane YUV 4:2:0
205 * In these formats, the component ordering is specified (Y, followed by U
206 * then V), but the exact Linear layout is undefined.
207 * These formats can only be used with a non-Linear modifier.
208 */
209 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
210 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
211
212 /*
213 * 2 plane RGB + A
214 * index 0 = RGB plane, same format as the corresponding non _A8 format has
215 * index 1 = A plane, [7:0] A
216 */
217 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
218 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
219 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
220 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
221 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
222 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
223 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
224 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
225
226 /*
227 * 2 plane YCbCr
228 * index 0 = Y plane, [7:0] Y
229 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
230 * or
231 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
232 */
233 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
234 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
235 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
236 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
239 /*
240 * 2 plane YCbCr
241 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
242 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
243 */
244 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
245
246 /*
247 * 2 plane YCbCr MSB aligned
248 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
249 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
250 */
251 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
252
253 /*
254 * 2 plane YCbCr MSB aligned
255 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
256 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
257 */
258 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
259
260 /*
261 * 2 plane YCbCr MSB aligned
262 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
263 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
264 */
265 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
266
267 /*
268 * 2 plane YCbCr MSB aligned
269 * index 0 = Y plane, [15:0] Y little endian
270 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
271 */
272 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
273
274 /* 2 plane YCbCr420.
275 * 3 10 bit components and 2 padding bits packed into 4 bytes.
276 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
277 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
278 */
279 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
280
281 /* 3 plane non-subsampled (444) YCbCr
282 * 16 bits per component, but only 10 bits are used and 6 bits are padded
283 * index 0: Y plane, [15:0] Y:x [10:6] little endian
284 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
285 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
286 */
287 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
288
289 /* 3 plane non-subsampled (444) YCrCb
290 * 16 bits per component, but only 10 bits are used and 6 bits are padded
291 * index 0: Y plane, [15:0] Y:x [10:6] little endian
292 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
293 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
294 */
295 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
296
297 /*
298 * 2 plane packed YCbCr
299 * 2x2 subsampled Cr:Cb plane 10 bits per channel
300 * index 0 = Y plane, [9:0] Y [10] little endian
301 * index 1 = Cr:Cb plane, [19:0] Cr:Cb [10:10] little endian
302 */
303 #define DRM_FORMAT_Y010 fourcc_code('Y', '0', '1', '0')
304
305 /*
306 * 3 plane YCbCr
307 * index 0: Y plane, [7:0] Y
308 * index 1: Cb plane, [7:0] Cb
309 * index 2: Cr plane, [7:0] Cr
310 * or
311 * index 1: Cr plane, [7:0] Cr
312 * index 2: Cb plane, [7:0] Cb
313 */
314 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
315 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
316 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
317 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
318 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
319 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
320 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
321 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
322 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
323 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
324
325
326 /*
327 * Format Modifiers:
328 *
329 * Format modifiers describe, typically, a re-ordering or modification
330 * of the data in a plane of an FB. This can be used to express tiled/
331 * swizzled formats, or compression, or a combination of the two.
332 *
333 * The upper 8 bits of the format modifier are a vendor-id as assigned
334 * below. The lower 56 bits are assigned as vendor sees fit.
335 */
336
337 /* Vendor Ids: */
338 #define DRM_FORMAT_MOD_NONE 0
339 #define DRM_FORMAT_MOD_VENDOR_NONE 0
340 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
341 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
342 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
343 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
344 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
345 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
346 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
347 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
348 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
349 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
350
351 /* add more to the end as needed */
352
353 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
354
355 #define fourcc_mod_code(vendor, val) \
356 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
357
358 /*
359 * Format Modifier tokens:
360 *
361 * When adding a new token please document the layout with a code comment,
362 * similar to the fourcc codes above. drm_fourcc.h is considered the
363 * authoritative source for all of these.
364 *
365 * Generic modifier names:
366 *
367 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
368 * for layouts which are common across multiple vendors. To preserve
369 * compatibility, in cases where a vendor-specific definition already exists and
370 * a generic name for it is desired, the common name is a purely symbolic alias
371 * and must use the same numerical value as the original definition.
372 *
373 * Note that generic names should only be used for modifiers which describe
374 * generic layouts (such as pixel re-ordering), which may have
375 * independently-developed support across multiple vendors.
376 *
377 * In future cases where a generic layout is identified before merging with a
378 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
379 * 'NONE' could be considered. This should only be for obvious, exceptional
380 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
381 * apply to a single vendor.
382 *
383 * Generic names should not be used for cases where multiple hardware vendors
384 * have implementations of the same standardised compression scheme (such as
385 * AFBC). In those cases, all implementations should use the same format
386 * modifier(s), reflecting the vendor of the standard.
387 */
388
389 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
390
391 /*
392 * Invalid Modifier
393 *
394 * This modifier can be used as a sentinel to terminate the format modifiers
395 * list, or to initialize a variable with an invalid modifier. It might also be
396 * used to report an error back to userspace for certain APIs.
397 */
398 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
399
400 /*
401 * Linear Layout
402 *
403 * Just plain linear layout. Note that this is different from no specifying any
404 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
405 * which tells the driver to also take driver-internal information into account
406 * and so might actually result in a tiled framebuffer.
407 */
408 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
409
410 /*
411 * Set to access the secure buffer
412 *
413 * The secure buffer is used to store DRM(Digital Right Management) contents.
414 * DMA needs special authority to access the secure buffer. This modifier can
415 * be set to allow the DMA to access the secure buffer. This can be used in
416 * combination with another modifier.
417 */
418 #define DRM_FORMAT_MOD_PROTECTION fourcc_mod_code(NONE, (1ULL << 51))
419
420 /* Intel framebuffer modifiers */
421
422 /*
423 * Intel X-tiling layout
424 *
425 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
426 * in row-major layout. Within the tile bytes are laid out row-major, with
427 * a platform-dependent stride. On top of that the memory can apply
428 * platform-depending swizzling of some higher address bits into bit6.
429 *
430 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
431 * On earlier platforms the is highly platforms specific and not useful for
432 * cross-driver sharing. It exists since on a given platform it does uniquely
433 * identify the layout in a simple way for i915-specific userspace, which
434 * facilitated conversion of userspace to modifiers. Additionally the exact
435 * format on some really old platforms is not known.
436 */
437 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
438
439 /*
440 * Intel Y-tiling layout
441 *
442 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
443 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
444 * chunks column-major, with a platform-dependent height. On top of that the
445 * memory can apply platform-depending swizzling of some higher address bits
446 * into bit6.
447 *
448 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
449 * On earlier platforms the is highly platforms specific and not useful for
450 * cross-driver sharing. It exists since on a given platform it does uniquely
451 * identify the layout in a simple way for i915-specific userspace, which
452 * facilitated conversion of userspace to modifiers. Additionally the exact
453 * format on some really old platforms is not known.
454 */
455 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
456
457 /*
458 * Intel Yf-tiling layout
459 *
460 * This is a tiled layout using 4Kb tiles in row-major layout.
461 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
462 * are arranged in four groups (two wide, two high) with column-major layout.
463 * Each group therefore consits out of four 256 byte units, which are also laid
464 * out as 2x2 column-major.
465 * 256 byte units are made out of four 64 byte blocks of pixels, producing
466 * either a square block or a 2:1 unit.
467 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
468 * in pixel depends on the pixel depth.
469 */
470 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
471
472 /*
473 * Intel color control surface (CCS) for render compression
474 *
475 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
476 * The main surface will be plane index 0 and must be Y/Yf-tiled,
477 * the CCS will be plane index 1.
478 *
479 * Each CCS tile matches a 1024x512 pixel area of the main surface.
480 * To match certain aspects of the 3D hardware the CCS is
481 * considered to be made up of normal 128Bx32 Y tiles, Thus
482 * the CCS pitch must be specified in multiples of 128 bytes.
483 *
484 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
485 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
486 * But that fact is not relevant unless the memory is accessed
487 * directly.
488 */
489 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
490 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
491
492 /*
493 * Intel color control surfaces (CCS) for Gen-12 render compression.
494 *
495 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
496 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
497 * main surface. In other words, 4 bits in CCS map to a main surface cache
498 * line pair. The main surface pitch is required to be a multiple of four
499 * Y-tile widths.
500 */
501 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
502
503 /*
504 * Intel color control surfaces (CCS) for Gen-12 media compression
505 *
506 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
507 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
508 * main surface. In other words, 4 bits in CCS map to a main surface cache
509 * line pair. The main surface pitch is required to be a multiple of four
510 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
511 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
512 * planes 2 and 3 for the respective CCS.
513 */
514 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
515
516 /*
517 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
518 *
519 * Macroblocks are laid in a Z-shape, and each pixel data is following the
520 * standard NV12 style.
521 * As for NV12, an image is the result of two frame buffers: one for Y,
522 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
523 * Alignment requirements are (for each buffer):
524 * - multiple of 128 pixels for the width
525 * - multiple of 32 pixels for the height
526 *
527 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
528 */
529 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
530
531 /*
532 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
533 *
534 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
535 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
536 * they correspond to their 16x16 luma block.
537 */
538 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
539
540 /*
541 * 4 plane YCbCr 4:2:0 10 bits per channel
542 * index 0: Y8 plane, [7:0] Y little endian
543 * index 1: Cr8:Cb8 plane, [15:0] CrCb little endian
544 * index 2: Y2 plane, [1:0] Y little endian
545 * index 3: Cr2:Cb2 plane, [3:0] CrCb little endian
546 */
547 #define DRM_FORMAT_MOD_SAMSUNG_YUV_8_2_SPLIT fourcc_mod_code(SAMSUNG, 3)
548
549 /*
550 * The colormap uses the color data generated by hardware instead of reading
551 * the data from the memory.
552 *
553 * It supports only solid color in BGRA8888 format. When it is used as
554 * a modifier, BGRA8888 format should be used and color value is passed through
555 * first handles[0].
556 */
557 #define DRM_FORMAT_MOD_SAMSUNG_COLORMAP fourcc_mod_code(SAMSUNG, 4)
558
559 /*
560 * Samsung Band Width Compression (SBWC) modifier
561 *
562 * SBWC is a specific lossless or lossy image compression protocol and format.
563 * It supports video image (YUV) compression to reduce the amount of data
564 * transferred between IP blocks. This modifier is used when to decode data or
565 * when to encode data through writeback.
566 */
567 #define SBWC_IDENTIFIER (1 << 4)
568 #define SBWC_FORMAT_MOD_BLOCK_SIZE_MASK (0xfULL << 5)
569 #define SBWC_BLOCK_SIZE_SET(blk_size) \
570 ((blk_size << 5) & SBWC_FORMAT_MOD_BLOCK_SIZE_MASK)
571 #define SBWC_BLOCK_SIZE_GET(modifier) \
572 (((modifier) & SBWC_FORMAT_MOD_BLOCK_SIZE_MASK) >> 5)
573 #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x2 (2ULL)
574 #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x3 (3ULL)
575 #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x4 (4ULL)
576 #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x5 (5ULL)
577 #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x6 (6ULL)
578
579 #define SBWC_FORMAT_MOD_LOSSY (1 << 12)
580
581 #define DRM_FORMAT_MOD_SAMSUNG_SBWC(blk_size) \
582 fourcc_mod_code(SAMSUNG, \
583 (SBWC_BLOCK_SIZE_SET(blk_size) | SBWC_IDENTIFIER))
584
585 /*
586 * Qualcomm Compressed Format
587 *
588 * Refers to a compressed variant of the base format that is compressed.
589 * Implementation may be platform and base-format specific.
590 *
591 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
592 * Pixel data pitch/stride is aligned with macrotile width.
593 * Pixel data height is aligned with macrotile height.
594 * Entire pixel data buffer is aligned with 4k(bytes).
595 */
596 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
597
598 /* Vivante framebuffer modifiers */
599
600 /*
601 * Vivante 4x4 tiling layout
602 *
603 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
604 * layout.
605 */
606 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
607
608 /*
609 * Vivante 64x64 super-tiling layout
610 *
611 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
612 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
613 * major layout.
614 *
615 * For more information: see
616 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
617 */
618 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
619
620 /*
621 * Vivante 4x4 tiling layout for dual-pipe
622 *
623 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
624 * different base address. Offsets from the base addresses are therefore halved
625 * compared to the non-split tiled layout.
626 */
627 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
628
629 /*
630 * Vivante 64x64 super-tiling layout for dual-pipe
631 *
632 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
633 * starts at a different base address. Offsets from the base addresses are
634 * therefore halved compared to the non-split super-tiled layout.
635 */
636 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
637
638 /* NVIDIA frame buffer modifiers */
639
640 /*
641 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
642 *
643 * Pixels are arranged in simple tiles of 16 x 16 bytes.
644 */
645 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
646
647 /*
648 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
649 * and Tegra GPUs starting with Tegra K1.
650 *
651 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
652 * based on the architecture generation. GOBs themselves are then arranged in
653 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
654 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
655 * a block depth or height of "4").
656 *
657 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
658 * in full detail.
659 *
660 * Macro
661 * Bits Param Description
662 * ---- ----- -----------------------------------------------------------------
663 *
664 * 3:0 h log2(height) of each block, in GOBs. Placed here for
665 * compatibility with the existing
666 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
667 *
668 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
669 * compatibility with the existing
670 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
671 *
672 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
673 * size). Must be zero.
674 *
675 * Note there is no log2(width) parameter. Some portions of the
676 * hardware support a block width of two gobs, but it is impractical
677 * to use due to lack of support elsewhere, and has no known
678 * benefits.
679 *
680 * 11:9 - Reserved (To support 2D-array textures with variable array stride
681 * in blocks, specified via log2(tile width in blocks)). Must be
682 * zero.
683 *
684 * 19:12 k Page Kind. This value directly maps to a field in the page
685 * tables of all GPUs >= NV50. It affects the exact layout of bits
686 * in memory and can be derived from the tuple
687 *
688 * (format, GPU model, compression type, samples per pixel)
689 *
690 * Where compression type is defined below. If GPU model were
691 * implied by the format modifier, format, or memory buffer, page
692 * kind would not need to be included in the modifier itself, but
693 * since the modifier should define the layout of the associated
694 * memory buffer independent from any device or other context, it
695 * must be included here.
696 *
697 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
698 * starting with Fermi GPUs. Additionally, the mapping between page
699 * kind and bit layout has changed at various points.
700 *
701 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
702 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
703 * 2 = Gob Height 8, Turing+ Page Kind mapping
704 * 3 = Reserved for future use.
705 *
706 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
707 * bit remapping step that occurs at an even lower level than the
708 * page kind and block linear swizzles. This causes the layout of
709 * surfaces mapped in those SOC's GPUs to be incompatible with the
710 * equivalent mapping on other GPUs in the same system.
711 *
712 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
713 * 1 = Desktop GPU and Tegra Xavier+ Layout
714 *
715 * 25:23 c Lossless Framebuffer Compression type.
716 *
717 * 0 = none
718 * 1 = ROP/3D, layout 1, exact compression format implied by Page
719 * Kind field
720 * 2 = ROP/3D, layout 2, exact compression format implied by Page
721 * Kind field
722 * 3 = CDE horizontal
723 * 4 = CDE vertical
724 * 5 = Reserved for future use
725 * 6 = Reserved for future use
726 * 7 = Reserved for future use
727 *
728 * 55:25 - Reserved for future use. Must be zero.
729 */
730 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
731 fourcc_mod_code(NVIDIA, (0x10 | \
732 ((h) & 0xf) | \
733 (((k) & 0xff) << 12) | \
734 (((g) & 0x3) << 20) | \
735 (((s) & 0x1) << 22) | \
736 (((c) & 0x7) << 23)))
737
738 /* To grandfather in prior block linear format modifiers to the above layout,
739 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
740 * with block-linear layouts, is remapped within drivers to the value 0xfe,
741 * which corresponds to the "generic" kind used for simple single-sample
742 * uncompressed color formats on Fermi - Volta GPUs.
743 */
744 static __inline__ __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)745 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
746 {
747 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
748 return modifier;
749 else
750 return modifier | (0xfe << 12);
751 }
752
753 /*
754 * 16Bx2 Block Linear layout, used by Tegra K1 and later
755 *
756 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
757 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
758 *
759 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
760 *
761 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
762 * Valid values are:
763 *
764 * 0 == ONE_GOB
765 * 1 == TWO_GOBS
766 * 2 == FOUR_GOBS
767 * 3 == EIGHT_GOBS
768 * 4 == SIXTEEN_GOBS
769 * 5 == THIRTYTWO_GOBS
770 *
771 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
772 * in full detail.
773 */
774 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
775 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
776
777 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
778 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
779 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
780 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
781 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
782 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
783 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
784 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
785 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
786 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
787 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
788 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
789
790 /*
791 * Some Broadcom modifiers take parameters, for example the number of
792 * vertical lines in the image. Reserve the lower 32 bits for modifier
793 * type, and the next 24 bits for parameters. Top 8 bits are the
794 * vendor code.
795 */
796 #define __fourcc_mod_broadcom_param_shift 8
797 #define __fourcc_mod_broadcom_param_bits 48
798 #define fourcc_mod_broadcom_code(val, params) \
799 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
800 #define fourcc_mod_broadcom_param(m) \
801 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
802 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
803 #define fourcc_mod_broadcom_mod(m) \
804 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
805 __fourcc_mod_broadcom_param_shift))
806
807 /*
808 * Broadcom VC4 "T" format
809 *
810 * This is the primary layout that the V3D GPU can texture from (it
811 * can't do linear). The T format has:
812 *
813 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
814 * pixels at 32 bit depth.
815 *
816 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
817 * 16x16 pixels).
818 *
819 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
820 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
821 * they're (TR, BR, BL, TL), where bottom left is start of memory.
822 *
823 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
824 * tiles) or right-to-left (odd rows of 4k tiles).
825 */
826 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
827
828 /*
829 * Broadcom SAND format
830 *
831 * This is the native format that the H.264 codec block uses. For VC4
832 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
833 *
834 * The image can be considered to be split into columns, and the
835 * columns are placed consecutively into memory. The width of those
836 * columns can be either 32, 64, 128, or 256 pixels, but in practice
837 * only 128 pixel columns are used.
838 *
839 * The pitch between the start of each column is set to optimally
840 * switch between SDRAM banks. This is passed as the number of lines
841 * of column width in the modifier (we can't use the stride value due
842 * to various core checks that look at it , so you should set the
843 * stride to width*cpp).
844 *
845 * Note that the column height for this format modifier is the same
846 * for all of the planes, assuming that each column contains both Y
847 * and UV. Some SAND-using hardware stores UV in a separate tiled
848 * image from Y to reduce the column height, which is not supported
849 * with these modifiers.
850 *
851 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
852 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
853 * wide, but as this is a 10 bpp format that translates to 96 pixels.
854 */
855
856 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
857 fourcc_mod_broadcom_code(2, v)
858 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
859 fourcc_mod_broadcom_code(3, v)
860 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
861 fourcc_mod_broadcom_code(4, v)
862 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
863 fourcc_mod_broadcom_code(5, v)
864
865 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
866 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
867 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
868 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
869 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
870 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
871 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
872 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
873
874 /* Broadcom UIF format
875 *
876 * This is the common format for the current Broadcom multimedia
877 * blocks, including V3D 3.x and newer, newer video codecs, and
878 * displays.
879 *
880 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
881 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
882 * stored in columns, with padding between the columns to ensure that
883 * moving from one column to the next doesn't hit the same SDRAM page
884 * bank.
885 *
886 * To calculate the padding, it is assumed that each hardware block
887 * and the software driving it knows the platform's SDRAM page size,
888 * number of banks, and XOR address, and that it's identical between
889 * all blocks using the format. This tiling modifier will use XOR as
890 * necessary to reduce the padding. If a hardware block can't do XOR,
891 * the assumption is that a no-XOR tiling modifier will be created.
892 */
893 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
894
895 /*
896 * Arm Framebuffer Compression (AFBC) modifiers
897 *
898 * AFBC is a proprietary lossless image compression protocol and format.
899 * It provides fine-grained random access and minimizes the amount of data
900 * transferred between IP blocks.
901 *
902 * AFBC has several features which may be supported and/or used, which are
903 * represented using bits in the modifier. Not all combinations are valid,
904 * and different devices or use-cases may support different combinations.
905 *
906 * Further information on the use of AFBC modifiers can be found in
907 * Documentation/gpu/afbc.rst
908 */
909
910 /*
911 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
912 * modifiers) denote the category for modifiers. Currently we have only two
913 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
914 * different categories.
915 */
916 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
917 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
918
919 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
920 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
921
922 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
923 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
924
925 /*
926 * AFBC superblock size
927 *
928 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
929 * size (in pixels) must be aligned to a multiple of the superblock size.
930 * Four lowest significant bits(LSBs) are reserved for block size.
931 *
932 * Where one superblock size is specified, it applies to all planes of the
933 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
934 * the first applies to the Luma plane and the second applies to the Chroma
935 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
936 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
937 */
938 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
939 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
940 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
941 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
942 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
943
944 /*
945 * AFBC lossless colorspace transform
946 *
947 * Indicates that the buffer makes use of the AFBC lossless colorspace
948 * transform.
949 */
950 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
951
952 /*
953 * AFBC block-split
954 *
955 * Indicates that the payload of each superblock is split. The second
956 * half of the payload is positioned at a predefined offset from the start
957 * of the superblock payload.
958 */
959 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
960
961 /*
962 * AFBC sparse layout
963 *
964 * This flag indicates that the payload of each superblock must be stored at a
965 * predefined position relative to the other superblocks in the same AFBC
966 * buffer. This order is the same order used by the header buffer. In this mode
967 * each superblock is given the same amount of space as an uncompressed
968 * superblock of the particular format would require, rounding up to the next
969 * multiple of 128 bytes in size.
970 */
971 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
972
973 /*
974 * AFBC copy-block restrict
975 *
976 * Buffers with this flag must obey the copy-block restriction. The restriction
977 * is such that there are no copy-blocks referring across the border of 8x8
978 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
979 */
980 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
981
982 /*
983 * AFBC tiled layout
984 *
985 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
986 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
987 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
988 * larger bpp formats. The order between the tiles is scan line.
989 * When the tiled layout is used, the buffer size (in pixels) must be aligned
990 * to the tile size.
991 */
992 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
993
994 /*
995 * AFBC solid color blocks
996 *
997 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
998 * can be reduced if a whole superblock is a single color.
999 */
1000 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1001
1002 /*
1003 * AFBC double-buffer
1004 *
1005 * Indicates that the buffer is allocated in a layout safe for front-buffer
1006 * rendering.
1007 */
1008 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1009
1010 /*
1011 * AFBC buffer content hints
1012 *
1013 * Indicates that the buffer includes per-superblock content hints.
1014 */
1015 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1016
1017 /* AFBC uncompressed storage mode
1018 *
1019 * Indicates that the buffer is using AFBC uncompressed storage mode.
1020 * In this mode all superblock payloads in the buffer use the uncompressed
1021 * storage mode, which is usually only used for data which cannot be compressed.
1022 * The buffer layout is the same as for AFBC buffers without USM set, this only
1023 * affects the storage mode of the individual superblocks. Note that even a
1024 * buffer without USM set may use uncompressed storage mode for some or all
1025 * superblocks, USM just guarantees it for all.
1026 */
1027 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1028
1029 /*
1030 * Arm 16x16 Block U-Interleaved modifier
1031 *
1032 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1033 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1034 * in the block are reordered.
1035 */
1036 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1037 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1038
1039 /*
1040 * Allwinner tiled modifier
1041 *
1042 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1043 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1044 * planes.
1045 *
1046 * With this tiling, the luminance samples are disposed in tiles representing
1047 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1048 * The pixel order in each tile is linear and the tiles are disposed linearly,
1049 * both in row-major order.
1050 */
1051 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1052
1053 /*
1054 * Amlogic Video Framebuffer Compression modifiers
1055 *
1056 * Amlogic uses a proprietary lossless image compression protocol and format
1057 * for their hardware video codec accelerators, either video decoders or
1058 * video input encoders.
1059 *
1060 * It considerably reduces memory bandwidth while writing and reading
1061 * frames in memory.
1062 *
1063 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1064 * per component YCbCr 420, single plane :
1065 * - DRM_FORMAT_YUV420_8BIT
1066 * - DRM_FORMAT_YUV420_10BIT
1067 *
1068 * The first 8 bits of the mode defines the layout, then the following 8 bits
1069 * defines the options changing the layout.
1070 *
1071 * Not all combinations are valid, and different SoCs may support different
1072 * combinations of layout and options.
1073 */
1074 #define __fourcc_mod_amlogic_layout_mask 0xff
1075 #define __fourcc_mod_amlogic_options_shift 8
1076 #define __fourcc_mod_amlogic_options_mask 0xff
1077
1078 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1079 fourcc_mod_code(AMLOGIC, \
1080 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1081 (((__options) & __fourcc_mod_amlogic_options_mask) \
1082 << __fourcc_mod_amlogic_options_shift))
1083
1084 /* Amlogic FBC Layouts */
1085
1086 /*
1087 * Amlogic FBC Basic Layout
1088 *
1089 * The basic layout is composed of:
1090 * - a body content organized in 64x32 superblocks with 4096 bytes per
1091 * superblock in default mode.
1092 * - a 32 bytes per 128x64 header block
1093 *
1094 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1095 */
1096 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1097
1098 /*
1099 * Amlogic FBC Scatter Memory layout
1100 *
1101 * Indicates the header contains IOMMU references to the compressed
1102 * frames content to optimize memory access and layout.
1103 *
1104 * In this mode, only the header memory address is needed, thus the
1105 * content memory organization is tied to the current producer
1106 * execution and cannot be saved/dumped neither transferrable between
1107 * Amlogic SoCs supporting this modifier.
1108 *
1109 * Due to the nature of the layout, these buffers are not expected to
1110 * be accessible by the user-space clients, but only accessible by the
1111 * hardware producers and consumers.
1112 *
1113 * The user-space clients should expect a failure while trying to mmap
1114 * the DMA-BUF handle returned by the producer.
1115 */
1116 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1117
1118 /* Amlogic FBC Layout Options Bit Mask */
1119
1120 /*
1121 * Amlogic FBC Memory Saving mode
1122 *
1123 * Indicates the storage is packed when pixel size is multiple of word
1124 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1125 * memory.
1126 *
1127 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1128 * the basic layout and 3200 bytes per 64x32 superblock combined with
1129 * the scatter layout.
1130 */
1131 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1132
1133 /* from 52 to 55 bit are reserved for AFBC encoder source informaton */
1134 #define AFBC_FORMAT_MOD_SOURCE_MASK (0xfULL << 52)
1135 #define AFBC_FORMAT_MOD_SOURCE_GPU (1ULL << 52)
1136 #define AFBC_FORMAT_MOD_SOURCE_G2D (2ULL << 52)
1137
1138 #if defined(__cplusplus)
1139 }
1140 #endif
1141
1142 #endif /* DRM_FOURCC_H */
1143