1/*
2 * Copyright (C) 2022 Google LLC
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7#define PLACEHOLDER	0xffffffff
8#define PLACEHOLDER2	PLACEHOLDER PLACEHOLDER
9#define PLACEHOLDER4	PLACEHOLDER2 PLACEHOLDER2
10
11#define PLACEHOLDER_CPU_MAP_CORE(n) core##n { cpu = <PLACEHOLDER>; };
12#define PLACEHOLDER_CPU_MAP_CLUSTER \
13	PLACEHOLDER_CPU_MAP_CORE(0) \
14	PLACEHOLDER_CPU_MAP_CORE(1) \
15	PLACEHOLDER_CPU_MAP_CORE(2) \
16	PLACEHOLDER_CPU_MAP_CORE(3) \
17	PLACEHOLDER_CPU_MAP_CORE(4) \
18	PLACEHOLDER_CPU_MAP_CORE(5) \
19	PLACEHOLDER_CPU_MAP_CORE(6) \
20	PLACEHOLDER_CPU_MAP_CORE(7) \
21	PLACEHOLDER_CPU_MAP_CORE(8) \
22	PLACEHOLDER_CPU_MAP_CORE(9)
23
24#define PLACEHOLDER_OPP_TABLE_ENTRY(n) opp##n { opp-hz = <PLACEHOLDER2>; };
25#define PLACEHOLDER_OPP_TABLE \
26	PLACEHOLDER_OPP_TABLE_ENTRY(1) \
27	PLACEHOLDER_OPP_TABLE_ENTRY(2) \
28	PLACEHOLDER_OPP_TABLE_ENTRY(3) \
29	PLACEHOLDER_OPP_TABLE_ENTRY(4) \
30	PLACEHOLDER_OPP_TABLE_ENTRY(5) \
31	PLACEHOLDER_OPP_TABLE_ENTRY(6) \
32	PLACEHOLDER_OPP_TABLE_ENTRY(7) \
33	PLACEHOLDER_OPP_TABLE_ENTRY(8) \
34	PLACEHOLDER_OPP_TABLE_ENTRY(9) \
35	PLACEHOLDER_OPP_TABLE_ENTRY(10) \
36	PLACEHOLDER_OPP_TABLE_ENTRY(11) \
37	PLACEHOLDER_OPP_TABLE_ENTRY(12) \
38	PLACEHOLDER_OPP_TABLE_ENTRY(13) \
39	PLACEHOLDER_OPP_TABLE_ENTRY(14) \
40	PLACEHOLDER_OPP_TABLE_ENTRY(15) \
41	PLACEHOLDER_OPP_TABLE_ENTRY(16) \
42	PLACEHOLDER_OPP_TABLE_ENTRY(17) \
43	PLACEHOLDER_OPP_TABLE_ENTRY(18) \
44	PLACEHOLDER_OPP_TABLE_ENTRY(19) \
45	PLACEHOLDER_OPP_TABLE_ENTRY(20)
46
47#define IRQ_BASE 4
48
49/dts-v1/;
50
51/ {
52	interrupt-parent = <&intc>;
53	compatible = "linux,dummy-virt";
54	#address-cells = <2>;
55	#size-cells = <2>;
56
57	chosen {
58		stdout-path = "/uart@3f8";
59		linux,pci-probe-only = <1>;
60		kaslr-seed = <PLACEHOLDER2>;
61		avf,strict-boot;
62		avf,new-instance;
63	};
64
65	memory {
66		device_type = "memory";
67		reg = <0x00 0x80000000 PLACEHOLDER2>;
68	};
69
70	reserved-memory {
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74		swiotlb: restricted_dma_reserved {
75			compatible = "restricted-dma-pool";
76			reg = <PLACEHOLDER4>;
77			size = <PLACEHOLDER2>;
78			alignment = <PLACEHOLDER2>;
79		};
80
81		dice {
82			compatible = "google,open-dice";
83			no-map;
84			reg = <PLACEHOLDER4>;
85		};
86	};
87
88	cpus {
89		#address-cells = <1>;
90		#size-cells = <0>;
91
92		cpu-map {
93			cluster0 { PLACEHOLDER_CPU_MAP_CLUSTER };
94			cluster1 { PLACEHOLDER_CPU_MAP_CLUSTER };
95			cluster2 { PLACEHOLDER_CPU_MAP_CLUSTER };
96		};
97
98		cpu0: cpu@0 {
99			device_type = "cpu";
100			compatible = "arm,armv8";
101			enable-method = "psci";
102			reg = <0x0>;
103			capacity-dmips-mhz = <PLACEHOLDER>;
104			operating-points-v2 = <&opp_table0>;
105			opp_table0: opp-table-0 {
106				compatible = "operating-points-v2";
107				PLACEHOLDER_OPP_TABLE
108			};
109		};
110		cpu1: cpu@1 {
111			device_type = "cpu";
112			compatible = "arm,armv8";
113			enable-method = "psci";
114			reg = <0x1>;
115			capacity-dmips-mhz = <PLACEHOLDER>;
116			operating-points-v2 = <&opp_table1>;
117			opp_table1: opp-table-1 {
118				compatible = "operating-points-v2";
119				PLACEHOLDER_OPP_TABLE
120			};
121		};
122		cpu2: cpu@2 {
123			device_type = "cpu";
124			compatible = "arm,armv8";
125			enable-method = "psci";
126			reg = <0x2>;
127			capacity-dmips-mhz = <PLACEHOLDER>;
128			operating-points-v2 = <&opp_table2>;
129			opp_table2: opp-table-2 {
130				compatible = "operating-points-v2";
131				PLACEHOLDER_OPP_TABLE
132			};
133		};
134		cpu3: cpu@3 {
135			device_type = "cpu";
136			compatible = "arm,armv8";
137			enable-method = "psci";
138			reg = <0x3>;
139			capacity-dmips-mhz = <PLACEHOLDER>;
140			operating-points-v2 = <&opp_table3>;
141			opp_table3: opp-table-3 {
142				compatible = "operating-points-v2";
143				PLACEHOLDER_OPP_TABLE
144			};
145		};
146		cpu4: cpu@4 {
147			device_type = "cpu";
148			compatible = "arm,armv8";
149			enable-method = "psci";
150			reg = <0x4>;
151			capacity-dmips-mhz = <PLACEHOLDER>;
152			operating-points-v2 = <&opp_table4>;
153			opp_table4: opp-table-4 {
154				compatible = "operating-points-v2";
155				PLACEHOLDER_OPP_TABLE
156			};
157		};
158		cpu5: cpu@5 {
159			device_type = "cpu";
160			compatible = "arm,armv8";
161			enable-method = "psci";
162			reg = <0x5>;
163			capacity-dmips-mhz = <PLACEHOLDER>;
164			operating-points-v2 = <&opp_table5>;
165			opp_table5: opp-table-5 {
166				compatible = "operating-points-v2";
167				PLACEHOLDER_OPP_TABLE
168			};
169		};
170		cpu6: cpu@6 {
171			device_type = "cpu";
172			compatible = "arm,armv8";
173			enable-method = "psci";
174			reg = <0x6>;
175			capacity-dmips-mhz = <PLACEHOLDER>;
176			operating-points-v2 = <&opp_table6>;
177			opp_table6: opp-table-6 {
178				compatible = "operating-points-v2";
179				PLACEHOLDER_OPP_TABLE
180			};
181		};
182		cpu7: cpu@7 {
183			device_type = "cpu";
184			compatible = "arm,armv8";
185			enable-method = "psci";
186			reg = <0x7>;
187			capacity-dmips-mhz = <PLACEHOLDER>;
188			operating-points-v2 = <&opp_table7>;
189			opp_table7: opp-table-7 {
190				compatible = "operating-points-v2";
191				PLACEHOLDER_OPP_TABLE
192			};
193		};
194		cpu8: cpu@8 {
195			device_type = "cpu";
196			compatible = "arm,armv8";
197			enable-method = "psci";
198			reg = <0x8>;
199			capacity-dmips-mhz = <PLACEHOLDER>;
200			operating-points-v2 = <&opp_table8>;
201			opp_table8: opp-table-8 {
202				compatible = "operating-points-v2";
203				PLACEHOLDER_OPP_TABLE
204			};
205		};
206		cpu9: cpu@9 {
207			device_type = "cpu";
208			compatible = "arm,armv8";
209			enable-method = "psci";
210			reg = <0x9>;
211			capacity-dmips-mhz = <PLACEHOLDER>;
212			operating-points-v2 = <&opp_table9>;
213			opp_table9: opp-table-9 {
214				compatible = "operating-points-v2";
215				PLACEHOLDER_OPP_TABLE
216			};
217		};
218		cpu10: cpu@a {
219			device_type = "cpu";
220			compatible = "arm,armv8";
221			enable-method = "psci";
222			reg = <0xa>;
223			capacity-dmips-mhz = <PLACEHOLDER>;
224			operating-points-v2 = <&opp_table10>;
225			opp_table10: opp-table-10 {
226				compatible = "operating-points-v2";
227				PLACEHOLDER_OPP_TABLE
228			};
229		};
230		cpu11: cpu@b {
231			device_type = "cpu";
232			compatible = "arm,armv8";
233			enable-method = "psci";
234			reg = <0xb>;
235			capacity-dmips-mhz = <PLACEHOLDER>;
236			operating-points-v2 = <&opp_table11>;
237			opp_table11: opp-table-11 {
238				compatible = "operating-points-v2";
239				PLACEHOLDER_OPP_TABLE
240			};
241		};
242		cpu12: cpu@c {
243			device_type = "cpu";
244			compatible = "arm,armv8";
245			enable-method = "psci";
246			reg = <0xc>;
247			capacity-dmips-mhz = <PLACEHOLDER>;
248			operating-points-v2 = <&opp_table12>;
249			opp_table12: opp-table-12 {
250				compatible = "operating-points-v2";
251				PLACEHOLDER_OPP_TABLE
252			};
253		};
254		cpu13: cpu@d {
255			device_type = "cpu";
256			compatible = "arm,armv8";
257			enable-method = "psci";
258			reg = <0xd>;
259			capacity-dmips-mhz = <PLACEHOLDER>;
260			operating-points-v2 = <&opp_table13>;
261			opp_table13: opp-table-13 {
262				compatible = "operating-points-v2";
263				PLACEHOLDER_OPP_TABLE
264			};
265		};
266		cpu14: cpu@e {
267			device_type = "cpu";
268			compatible = "arm,armv8";
269			enable-method = "psci";
270			reg = <0xe>;
271			capacity-dmips-mhz = <PLACEHOLDER>;
272			operating-points-v2 = <&opp_table14>;
273			opp_table14: opp-table-14 {
274				compatible = "operating-points-v2";
275				PLACEHOLDER_OPP_TABLE
276			};
277		};
278		cpu15: cpu@f {
279			device_type = "cpu";
280			compatible = "arm,armv8";
281			enable-method = "psci";
282			reg = <0xf>;
283			capacity-dmips-mhz = <PLACEHOLDER>;
284			operating-points-v2 = <&opp_table15>;
285			opp_table15: opp-table-15 {
286				compatible = "operating-points-v2";
287				PLACEHOLDER_OPP_TABLE
288			};
289		};
290	};
291
292	intc: intc {
293		compatible = "arm,gic-v3";
294		#address-cells = <2>;
295		#size-cells = <2>;
296		#interrupt-cells = <3>;
297		interrupt-controller;
298		reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
299	};
300
301	timer {
302		compatible = "arm,armv8-timer";
303		always-on;
304		/* The IRQ type needs to be OR-ed with the CPU mask */
305		interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
306		              GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
307			      GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
308			      GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
309	};
310
311	uart@3f8 {
312		compatible = "ns16550a";
313		reg = <0x00 0x3f8 0x00 0x8>;
314		clock-frequency = <0x1c2000>;
315		interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
316	};
317
318	uart@2f8 {
319		compatible = "ns16550a";
320		reg = <0x00 0x2f8 0x00 0x8>;
321		clock-frequency = <0x1c2000>;
322		interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
323	};
324
325	uart@3e8 {
326		compatible = "ns16550a";
327		reg = <0x00 0x3e8 0x00 0x8>;
328		clock-frequency = <0x1c2000>;
329		interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
330	};
331
332	uart@2e8 {
333		compatible = "ns16550a";
334		reg = <0x00 0x2e8 0x00 0x8>;
335		clock-frequency = <0x1c2000>;
336		interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
337	};
338
339	psci {
340		compatible = "arm,psci-1.0";
341		method = "hvc";
342	};
343
344	pci {
345		compatible = "pci-host-cam-generic";
346		device_type = "pci";
347		#address-cells = <3>;
348		#size-cells = <2>;
349		#interrupt-cells = <1>;
350		dma-coherent;
351		memory-region = <&swiotlb>;
352		ranges = <
353			0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
354			0x3000000 PLACEHOLDER2   PLACEHOLDER2   PLACEHOLDER2
355		>;
356		bus-range = <0x00 0x00>;
357		reg = <0x00 0x10000 0x00 0x1000000>;
358		interrupt-map = <
359			0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH
360			0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH
361			0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH
362			0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH
363			0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH
364			0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH
365			0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH
366			0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH
367			0x4800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 8) IRQ_TYPE_LEVEL_HIGH
368			0x5000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 9) IRQ_TYPE_LEVEL_HIGH
369			0x5800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 10) IRQ_TYPE_LEVEL_HIGH
370			0x6000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 11) IRQ_TYPE_LEVEL_HIGH
371			0x6800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 12) IRQ_TYPE_LEVEL_HIGH
372			0x7000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 13) IRQ_TYPE_LEVEL_HIGH
373			0x7800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 14) IRQ_TYPE_LEVEL_HIGH
374			0x8000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 15) IRQ_TYPE_LEVEL_HIGH
375		>;
376		interrupt-map-mask = <0xf800 0x0 0x0 0x7
377				      0xf800 0x0 0x0 0x7
378				      0xf800 0x0 0x0 0x7
379				      0xf800 0x0 0x0 0x7
380				      0xf800 0x0 0x0 0x7
381				      0xf800 0x0 0x0 0x7
382				      0xf800 0x0 0x0 0x7
383				      0xf800 0x0 0x0 0x7
384				      0xf800 0x0 0x0 0x7
385				      0xf800 0x0 0x0 0x7
386				      0xf800 0x0 0x0 0x7
387				      0xf800 0x0 0x0 0x7
388				      0xf800 0x0 0x0 0x7
389				      0xf800 0x0 0x0 0x7
390				      0xf800 0x0 0x0 0x7
391				      0xf800 0x0 0x0 0x7>;
392	};
393
394	clk: pclk@3M {
395		compatible = "fixed-clock";
396		clock-frequency = <0x2fefd8>;
397		#clock-cells = <0>;
398	};
399
400	rtc@2000 {
401		compatible = "arm,primecell";
402		arm,primecell-periphid = <0x41030>;
403		reg = <0x00 0x2000 0x00 0x1000>;
404		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
405		clock-names = "apb_pclk";
406		clocks = <&clk>;
407	};
408
409	vmwdt@3000 {
410		compatible = "qemu,vcpu-stall-detector";
411		reg = <0x00 0x3000 0x00 0x1000>;
412		clock-frequency = <10>;
413		timeout-sec = <8>;
414	};
415
416	cpufreq {
417		compatible = "virtual,android-v-only-cpufreq";
418		reg = <0x0 0x1040000 PLACEHOLDER2>;
419	};
420
421	// Keep pvIOMMUs at the last for making test happy.
422	// Otherwise, phandle of other nodes are changed when unused pvIOMMU nodes
423	// are removed, so hardcoded phandles in test data would mismatch.
424	pviommu_0: pviommu0 {
425		compatible = "pkvm,pviommu";
426		id = <PLACEHOLDER>;
427		#iommu-cells = <1>;
428	};
429
430	pviommu_1: pviommu1 {
431		compatible = "pkvm,pviommu";
432		id = <PLACEHOLDER>;
433		#iommu-cells = <1>;
434	};
435
436	pviommu_2: pviommu2 {
437		compatible = "pkvm,pviommu";
438		id = <PLACEHOLDER>;
439		#iommu-cells = <1>;
440	};
441
442	pviommu_3: pviommu3 {
443		compatible = "pkvm,pviommu";
444		id = <PLACEHOLDER>;
445		#iommu-cells = <1>;
446	};
447
448	pviommu_4: pviommu4 {
449		compatible = "pkvm,pviommu";
450		id = <PLACEHOLDER>;
451		#iommu-cells = <1>;
452	};
453
454	pviommu_5: pviommu5 {
455		compatible = "pkvm,pviommu";
456		id = <PLACEHOLDER>;
457		#iommu-cells = <1>;
458	};
459
460	pviommu_6: pviommu6 {
461		compatible = "pkvm,pviommu";
462		id = <PLACEHOLDER>;
463		#iommu-cells = <1>;
464	};
465
466	pviommu_7: pviommu7 {
467		compatible = "pkvm,pviommu";
468		id = <PLACEHOLDER>;
469		#iommu-cells = <1>;
470	};
471
472	pviommu_8: pviommu8 {
473		compatible = "pkvm,pviommu";
474		id = <PLACEHOLDER>;
475		#iommu-cells = <1>;
476	};
477
478	pviommu_9: pviommu9 {
479		compatible = "pkvm,pviommu";
480		id = <PLACEHOLDER>;
481		#iommu-cells = <1>;
482	};
483
484	// Do not add new node below
485};
486