1/dts-v1/;
2
3// This is generated manually by removing unassigned pvIOMMU nodes
4// from patched platform.dts.
5
6/ {
7	interrupt-parent = <0x01>;
8	compatible = "linux,dummy-virt";
9	#address-cells = <0x02>;
10	#size-cells = <0x02>;
11
12	chosen {
13		bootargs = "panic=-1 crashkernel=31M";
14		linux,initrd-end = <0x811d6cb8>;
15		linux,initrd-start = <0x81000000>;
16		stdout-path = "/uart@3f8";
17		1,pci-probe-only = <0x01>;
18		kaslr-seed = <0x00 0x00>;
19		avf,strict-boot;
20		avf,new-instance;
21	};
22
23	memory {
24		device_type = "memory";
25		reg = <0x00 0x80000000 0x00 0x10000000>;
26	};
27
28	reserved-memory {
29		#address-cells = <0x02>;
30		#size-cells = <0x02>;
31		ranges;
32
33		restricted_dma_reserved {
34			compatible = "restricted-dma-pool";
35			size = <0x00 0xe00000>;
36			alignment = <0x00 0x1000>;
37			phandle = <0x02>;
38		};
39
40		dice {
41			compatible = "google,open-dice";
42			no-map;
43			reg = <0x00 0x7fe25000 0x00 0x1000>;
44		};
45	};
46
47	cpus {
48		#address-cells = <0x01>;
49		#size-cells = <0x00>;
50
51		cpu@0 {
52			device_type = "cpu";
53			compatible = "arm,armv8";
54			enable-method = "psci";
55			reg = <0x00>;
56		};
57	};
58
59	intc {
60		compatible = "arm,gic-v3";
61		#address-cells = <0x02>;
62		#size-cells = <0x02>;
63		#interrupt-cells = <0x03>;
64		interrupt-controller;
65		reg = <0x00 0x3fff0000 0x00 0x10000 0x00 0x3ffd0000 0x00 0x20000>;
66		phandle = <0x01>;
67	};
68
69	timer {
70		compatible = "arm,armv8-timer";
71		always-on;
72		interrupts = <0x01 0x0d 0x108 0x01 0x0e 0x108 0x01 0x0b 0x108 0x01 0x0a 0x108>;
73	};
74
75	uart@2e8 {
76		compatible = "ns16550a";
77		reg = <0x00 0x2e8 0x00 0x08>;
78		clock-frequency = <0x1c2000>;
79		interrupts = <0x00 0x02 0x01>;
80	};
81
82	uart@2f8 {
83		compatible = "ns16550a";
84		reg = <0x00 0x2f8 0x00 0x08>;
85		clock-frequency = <0x1c2000>;
86		interrupts = <0x00 0x02 0x01>;
87	};
88
89	uart@3e8 {
90		compatible = "ns16550a";
91		reg = <0x00 0x3e8 0x00 0x08>;
92		clock-frequency = <0x1c2000>;
93		interrupts = <0x00 0x00 0x01>;
94	};
95
96	uart@3f8 {
97		compatible = "ns16550a";
98		reg = <0x00 0x3f8 0x00 0x08>;
99		clock-frequency = <0x1c2000>;
100		interrupts = <0x00 0x00 0x01>;
101	};
102
103	psci {
104		compatible = "arm,psci-1.0";
105		method = "hvc";
106	};
107
108	pci {
109		compatible = "pci-host-cam-generic";
110		device_type = "pci";
111		#address-cells = <0x03>;
112		#size-cells = <0x02>;
113		#interrupt-cells = <0x01>;
114		dma-coherent;
115		memory-region = <0x02>;
116		ranges = <0x3000000 0x00 0x2000000 0x00 0x2000000 0x00 0x2000000 0x3000000 0x00 0x90800000 0x00 0x90800000 0xff 0x6f800000>;
117		bus-range = <0x00 0x00>;
118		reg = <0x00 0x10000 0x00 0x1000000>;
119		interrupt-map = <0x800 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x04 0x04 0x1000 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x05 0x04 0x1800 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x06 0x04 0x2000 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x07 0x04 0x2800 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x08 0x04 0x3000 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x09 0x04 0x3800 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x0a 0x04 0x4000 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x0b 0x04 0x4800 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x0c 0x04>;
120		interrupt-map-mask = <0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07 0xf800 0x00 0x00 0x07>;
121	};
122
123	pclk@3M {
124		compatible = "fixed-clock";
125		clock-frequency = <0x2fefd8>;
126		#clock-cells = <0x00>;
127		phandle = <0x03>;
128	};
129
130	rtc@2000 {
131		compatible = "arm,primecell";
132		arm,primecell-periphid = <0x41030>;
133		reg = <0x00 0x2000 0x00 0x1000>;
134		interrupts = <0x00 0x01 0x04>;
135		clock-names = "apb_pclk";
136		clocks = <0x03>;
137	};
138
139	vmwdt@3000 {
140		compatible = "qemu,vcpu-stall-detector";
141		reg = <0x00 0x3000 0x00 0x1000>;
142		clock-frequency = <0x0a>;
143		timeout-sec = <0x08>;
144	};
145
146	__symbols__ {
147		swiotlb = "/reserved-memory/restricted_dma_reserved";
148		intc = "/intc";
149		clk = "/pclk@3M";
150	};
151};
152