| /art/compiler/utils/arm/ |
| D | assembler_arm32.cc | 29 Condition cond) { in and_()
35 Condition cond) { in eor()
41 Condition cond) { in sub()
46 Condition cond) { in rsb()
51 Condition cond) { in rsbs()
57 Condition cond) { in add()
63 Condition cond) { in adds()
69 Condition cond) { in subs()
75 Condition cond) { in adc()
81 Condition cond) { in sbc()
[all …]
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| D | assembler_thumb2.cc | 29 Condition cond) { in and_()
35 Condition cond) { in eor()
41 Condition cond) { in sub()
47 Condition cond) { in rsb()
53 Condition cond) { in rsbs()
59 Condition cond) { in add()
65 Condition cond) { in adds()
71 Condition cond) { in subs()
77 Condition cond) { in adc()
83 Condition cond) { in sbc()
[all …]
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| D | assembler_thumb2.h | 432 void CheckCondition(Condition cond) { in CheckCondition()
444 void CheckConditionLastIt(Condition cond) { in CheckConditionLastIt()
598 void ResetTypeAndCondition(Type type, Condition cond) { in ResetTypeAndCondition()
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| /art/test/112-double-math/src/ |
| D | Main.java | 18 public static double cond_neg_double(double value, boolean cond) { in cond_neg_double()
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
385 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT()
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| /art/disassembler/ |
| D | disassembler_arm.cc | 75 void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { in DumpCond()
246 uint32_t cond = (instruction >> 28) & 0xf; in DumpArm() local
1175 uint32_t cond = (instr >> 22) & 0xF; in DumpThumb32() local
1211 uint32_t cond = (instr >> 22) & 0xF; in DumpThumb32() local
1807 uint32_t cond = (instr >> 8) & 0xF; in DumpThumb16() local
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 72 void Arm64Assembler::AddConstant(Register rd, int32_t value, Condition cond) { in AddConstant()
77 Condition cond) { in AddConstant()
197 Condition cond) { in LoadImmediate()
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 72 X86ConditionCode X86ConditionEncoding(ConditionCode cond) { in X86ConditionEncoding()
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch()
1252 LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT()
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| D | utility_x86.cc | 890 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
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| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 123 inline Condition ARMCondition(IfCondition cond) { in ARMCondition()
137 inline Condition ARMOppositeCondition(IfCondition cond) { in ARMOppositeCondition()
549 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
559 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
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| D | code_generator_x86_64.cc | 127 inline Condition X86_64Condition(IfCondition cond) { in X86_64Condition()
388 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
398 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
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| D | code_generator_x86.cc | 120 inline Condition X86Condition(IfCondition cond) { in X86Condition()
507 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
517 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
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| D | builder.cc | 567 #define IF_XX(comparison, cond) \ in AnalyzeDexInstruction() argument
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch()
287 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch()
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| /art/compiler/llvm/ |
| D | ir_builder.h | 186 ::llvm::BranchInst* CreateCondBr(::llvm::Value *cond, in CreateCondBr()
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
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| /art/compiler/dex/quick/ |
| D | gen_common.cc | 223 ConditionCode cond; in GenCompareAndBranch() local
286 ConditionCode cond; in GenCompareZeroAndBranch() local
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| D | codegen_util.cc | 1210 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
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