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Searched refs:ArmMir2Lir (Results 1 – 7 of 7) sorted by relevance

/art/compiler/dex/quick/arm/
Dtarget_arm.cc69 RegLocation ArmMir2Lir::LocCReturn() { in LocCReturn()
73 RegLocation ArmMir2Lir::LocCReturnRef() { in LocCReturnRef()
77 RegLocation ArmMir2Lir::LocCReturnWide() { in LocCReturnWide()
81 RegLocation ArmMir2Lir::LocCReturnFloat() { in LocCReturnFloat()
85 RegLocation ArmMir2Lir::LocCReturnDouble() { in LocCReturnDouble()
90 RegStorage ArmMir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg()
121 RegStorage ArmMir2Lir::GetArgMappingToPhysicalReg(int arg_num) { in GetArgMappingToPhysicalReg()
138 ResourceMask ArmMir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon()
142 constexpr ResourceMask ArmMir2Lir::GetRegMaskArm(RegStorage reg) { in GetRegMaskArm()
149 constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list) { in EncodeArmRegList()
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Dutility_arm.cc72 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { in LoadFPConstantValue()
120 int ArmMir2Lir::ModifiedImmediate(uint32_t value) { in ModifiedImmediate()
149 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { in InexpensiveConstantInt()
153 bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat()
157 bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong()
161 bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { in InexpensiveConstantDouble()
173 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
207 LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
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Dint_arm.cc28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
71 void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) { in UpdateIT()
99 void ArmMir2Lir::OpEndIT(LIR* it) { in OpEndIT()
122 void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { in GenCmpLong()
155 void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, in GenFusedLongCmpImmBranch()
206 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
230 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect()
305 void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch()
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
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Dfp_arm.cc23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat()
69 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
116 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { in GenConversion()
214 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch()
265 void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
323 void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat()
331 void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { in GenNegDouble()
357 bool ArmMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
375 bool ArmMir2Lir::GenInlinedAbsDouble(CallInfo* info) { in GenInlinedAbsDouble()
402 bool ArmMir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
Dcall_arm.cc46 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargeSparseSwitch()
94 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargePackedSwitch()
150 void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { in GenFillArrayData()
179 void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { in GenMonitorEnter()
250 void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { in GenMonitorExit()
313 void ArmMir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException()
327 void ArmMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { in MarkGCCard()
340 void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence()
471 void ArmMir2Lir::GenExitSequence() { in GenExitSequence()
498 void ArmMir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence()
Dassemble_arm.cc79 const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = {
1041 void ArmMir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in ReplaceFixup()
1052 void ArmMir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in InsertFixupBefore()
1070 uint8_t* ArmMir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs()
1210 void ArmMir2Lir::AssembleLIR() { in AssembleLIR()
1631 size_t ArmMir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize()
1637 uint32_t ArmMir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { in LinkFixupInsns()
1671 void ArmMir2Lir::AssignDataOffsets() { in AssignDataOffsets()
Dcodegen_arm.h25 class ArmMir2Lir FINAL : public Mir2Lir {
27 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);