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Searched refs:cond (Results 1 – 25 of 31) sorted by relevance

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/art/compiler/utils/arm/
Dassembler_arm32.cc29 Condition cond) { in and_() argument
30 EmitType01(cond, so.type(), AND, 0, rn, rd, so); in and_()
35 Condition cond) { in eor() argument
36 EmitType01(cond, so.type(), EOR, 0, rn, rd, so); in eor()
41 Condition cond) { in sub() argument
42 EmitType01(cond, so.type(), SUB, 0, rn, rd, so); in sub()
46 Condition cond) { in rsb() argument
47 EmitType01(cond, so.type(), RSB, 0, rn, rd, so); in rsb()
51 Condition cond) { in rsbs() argument
52 EmitType01(cond, so.type(), RSB, 1, rn, rd, so); in rsbs()
[all …]
Dassembler_arm32.h43 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
45 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
47 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
48 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
50 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
51 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
53 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
55 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
57 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
59 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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Dassembler_thumb2.h65 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
67 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
70 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
72 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
73 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
75 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
77 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
79 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
81 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
[all …]
Dassembler_thumb2.cc29 Condition cond) { in and_() argument
30 EmitDataProcessing(cond, AND, 0, rn, rd, so); in and_()
35 Condition cond) { in eor() argument
36 EmitDataProcessing(cond, EOR, 0, rn, rd, so); in eor()
41 Condition cond) { in sub() argument
42 EmitDataProcessing(cond, SUB, 0, rn, rd, so); in sub()
47 Condition cond) { in rsb() argument
48 EmitDataProcessing(cond, RSB, 0, rn, rd, so); in rsb()
53 Condition cond) { in rsbs() argument
54 EmitDataProcessing(cond, RSB, 1, rn, rd, so); in rsbs()
[all …]
Dassembler_arm.h363 virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
365 virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
367 virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
368 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
370 virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
371 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
373 virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
375 virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
377 virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
379 virtual void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
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/art/test/112-double-math/src/
DMain.java18 public static double cond_neg_double(double value, boolean cond) { in cond_neg_double() argument
19 return cond ? -value : value; in cond_neg_double()
/art/compiler/dex/quick/
Dgen_common.cc223 ConditionCode cond; in GenCompareAndBranch() local
226 cond = kCondEq; in GenCompareAndBranch()
229 cond = kCondNe; in GenCompareAndBranch()
232 cond = kCondLt; in GenCompareAndBranch()
235 cond = kCondGe; in GenCompareAndBranch()
238 cond = kCondGt; in GenCompareAndBranch()
241 cond = kCondLe; in GenCompareAndBranch()
244 cond = static_cast<ConditionCode>(0); in GenCompareAndBranch()
253 cond = FlipComparisonOrder(cond); in GenCompareAndBranch()
265 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); in GenCompareAndBranch()
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Dmir_to_lir.h1138 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
1387 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
1388 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value,
1393 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0;
/art/compiler/dex/quick/mips/
Dint_mips.cc65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
71 switch (cond) { in OpCmpBranch()
112 LOG(FATAL) << "No support for ConditionCode: " << cond; in OpCmpBranch()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch() argument
137 branch = OpCmpBranch(cond, reg, t_reg, target); in OpCmpImmBranch()
142 switch (cond) { in OpCmpImmBranch()
154 branch = OpCmpBranch(cond, reg, t_reg, target); in OpCmpImmBranch()
385 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT() argument
Dcodegen_mips.h137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
138 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
142 LIR* OpIT(ConditionCode cond, const char* guide);
/art/compiler/utils/arm64/
Dassembler_arm64.cc72 void Arm64Assembler::AddConstant(Register rd, int32_t value, Condition cond) { in AddConstant() argument
73 AddConstant(rd, rd, value, cond); in AddConstant()
77 Condition cond) { in AddConstant() argument
78 if ((cond == AL) || (cond == NV)) { in AddConstant()
88 ___ Csel(reg_x(rd), temp, reg_x(rd), COND_OP(cond)); in AddConstant()
197 Condition cond) { in LoadImmediate() argument
198 if ((cond == AL) || (cond == NV)) { in LoadImmediate()
208 ___ Csel(reg_x(dest), temp, reg_x(dest), COND_OP(cond)); in LoadImmediate()
210 ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), COND_OP(cond)); in LoadImmediate()
Dassembler_arm64.h228 void LoadImmediate(Register dest, int32_t value, Condition cond = AL);
235 void AddConstant(Register rd, int32_t value, Condition cond = AL);
236 void AddConstant(Register rd, Register rn, int32_t value, Condition cond = AL);
/art/disassembler/
Ddisassembler_arm.cc75 void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { in DumpCond() argument
76 if (cond < 15) { in DumpCond()
77 os << kConditionCodeNames[cond]; in DumpCond()
79 os << "Unexpected condition: " << cond; in DumpCond()
246 uint32_t cond = (instruction >> 28) & 0xf; in DumpArm() local
356 opcode += kConditionCodeNames[cond]; in DumpArm()
1175 uint32_t cond = (instr >> 22) & 0xF; in DumpThumb32() local
1179 DumpCond(opcode, cond); in DumpThumb32()
1211 uint32_t cond = (instr >> 22) & 0xF; in DumpThumb32() local
1221 DumpCond(opcode, cond); in DumpThumb32()
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Ddisassembler_arm.h42 void DumpCond(std::ostream& os, uint32_t cond);
/art/compiler/dex/quick/arm/
Dcodegen_arm.h139 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
140 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
144 LIR* OpIT(ConditionCode cond, const char* guide);
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
206 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
210 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
31 return OpCondBranch(cond, target); in OpCmpBranch()
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch() argument
262 ArmConditionCode arm_cond = ArmConditionEncoding(cond); in OpCmpImmBranch()
287 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch() argument
297 LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target); in OpCmpMemImmBranch()
/art/compiler/optimizing/
Dcode_generator_arm.cc123 inline Condition ARMCondition(IfCondition cond) { in ARMCondition() argument
124 switch (cond) { in ARMCondition()
137 inline Condition ARMOppositeCondition(IfCondition cond) { in ARMOppositeCondition() argument
138 switch (cond) { in ARMOppositeCondition()
549 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
550 DCHECK(cond->IsCondition()); in VisitIf()
551 HCondition* condition = cond->AsCondition(); in VisitIf()
559 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
560 DCHECK(cond->IsCondition()); in VisitIf()
561 HCondition* condition = cond->AsCondition(); in VisitIf()
Dcode_generator_x86_64.cc127 inline Condition X86_64Condition(IfCondition cond) { in X86_64Condition() argument
128 switch (cond) { in X86_64Condition()
388 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
389 DCHECK(cond->IsCondition()); in VisitIf()
390 HCondition* condition = cond->AsCondition(); in VisitIf()
398 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
399 DCHECK(cond->IsCondition()); in VisitIf()
400 HCondition* condition = cond->AsCondition(); in VisitIf()
Dcode_generator_x86.cc120 inline Condition X86Condition(IfCondition cond) { in X86Condition() argument
121 switch (cond) { in X86Condition()
507 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
508 DCHECK(cond->IsCondition()); in VisitIf()
509 HCondition* condition = cond->AsCondition(); in VisitIf()
517 HInstruction* cond = if_instr->InputAt(0); in VisitIf() local
518 DCHECK(cond->IsCondition()); in VisitIf()
519 HCondition* condition = cond->AsCondition(); in VisitIf()
Dbuilder.cc567 #define IF_XX(comparison, cond) \ in AnalyzeDexInstruction() argument
568 case Instruction::IF_##cond: If_22t<comparison>(instruction, dex_offset); break; \ in AnalyzeDexInstruction()
569 case Instruction::IF_##cond##Z: If_21t<comparison>(instruction, dex_offset); break in AnalyzeDexInstruction()
/art/compiler/llvm/
Dir_builder.h186 ::llvm::BranchInst* CreateCondBr(::llvm::Value *cond, in CreateCondBr() argument
190 ::llvm::BranchInst* branch_inst = CreateCondBr(cond, true_bb, false_bb); in CreateCondBr()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h264 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
265 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
269 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
780 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
Dint_x86.cc72 X86ConditionCode X86ConditionEncoding(ConditionCode cond) { in X86ConditionEncoding() argument
73 switch (cond) { in X86ConditionEncoding()
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
98 X86ConditionCode cc = X86ConditionEncoding(cond); in OpCmpBranch()
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch() argument
107 if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { in OpCmpImmBranch()
117 X86ConditionCode cc = X86ConditionEncoding(cond); in OpCmpImmBranch()
1252 LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT() argument
/art/runtime/
Ddebugger.h63 cond("a DebugInvokeReq condition variable", lock) { in DebugInvokeReq()
89 ConditionVariable cond GUARDED_BY(lock);

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