1 /*
2  * Copyright (C) 2011 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_
18 #define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_
19 
20 #include "arm64_lir.h"
21 #include "dex/compiler_internals.h"
22 
23 #include <map>
24 
25 namespace art {
26 
27 class Arm64Mir2Lir FINAL : public Mir2Lir {
28  protected:
29   // TODO: consolidate 64-bit target support.
30   class InToRegStorageMapper {
31    public:
32     virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0;
~InToRegStorageMapper()33     virtual ~InToRegStorageMapper() {}
34   };
35 
36   class InToRegStorageArm64Mapper : public InToRegStorageMapper {
37    public:
InToRegStorageArm64Mapper()38     InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {}
~InToRegStorageArm64Mapper()39     virtual ~InToRegStorageArm64Mapper() {}
40     virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref);
41    private:
42     int cur_core_reg_;
43     int cur_fp_reg_;
44   };
45 
46   class InToRegStorageMapping {
47    public:
InToRegStorageMapping()48     InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false),
49     initialized_(false) {}
50     void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper);
GetMaxMappedIn()51     int GetMaxMappedIn() { return max_mapped_in_; }
IsThereStackMapped()52     bool IsThereStackMapped() { return is_there_stack_mapped_; }
53     RegStorage Get(int in_position);
IsInitialized()54     bool IsInitialized() { return initialized_; }
55    private:
56     std::map<int, RegStorage> mapping_;
57     int max_mapped_in_;
58     bool is_there_stack_mapped_;
59     bool initialized_;
60   };
61 
62  public:
63   Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
64 
65   // Required for target - codegen helpers.
66   bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
67                           RegLocation rl_dest, int lit) OVERRIDE;
68   bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
69                         RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
70   bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div,
71                           RegLocation rl_src, RegLocation rl_dest, int64_t lit);
72   bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
73   LIR* CheckSuspendUsingLoad() OVERRIDE;
74   RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE;
75   LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
76                     OpSize size, VolatileKind is_volatile) OVERRIDE;
77   LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
78                    VolatileKind is_volatile) OVERRIDE;
79   LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
80                        OpSize size) OVERRIDE;
81   LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale)
82       OVERRIDE;
83   LIR* LoadConstantNoClobber(RegStorage r_dest, int value) OVERRIDE;
84   LIR* LoadConstantWide(RegStorage r_dest, int64_t value) OVERRIDE;
85   LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
86                      VolatileKind is_volatile) OVERRIDE;
87   LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile)
88       OVERRIDE;
89   LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
90                         OpSize size) OVERRIDE;
91   LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE;
92   void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE;
93   LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
94                          int offset, int check_value, LIR* target, LIR** compare) OVERRIDE;
95 
96   // Required for target - register utilities.
97   RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE;
TargetReg(SpecialTargetRegister symbolic_reg,WideKind wide_kind)98   RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE {
99     if (wide_kind == kWide || wide_kind == kRef) {
100       return As64BitReg(TargetReg(symbolic_reg));
101     } else {
102       return Check32BitReg(TargetReg(symbolic_reg));
103     }
104   }
TargetPtrReg(SpecialTargetRegister symbolic_reg)105   RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE {
106     return As64BitReg(TargetReg(symbolic_reg));
107   }
108   RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE;
109   RegLocation GetReturnAlt() OVERRIDE;
110   RegLocation GetReturnWideAlt() OVERRIDE;
111   RegLocation LocCReturn() OVERRIDE;
112   RegLocation LocCReturnRef() OVERRIDE;
113   RegLocation LocCReturnDouble() OVERRIDE;
114   RegLocation LocCReturnFloat() OVERRIDE;
115   RegLocation LocCReturnWide() OVERRIDE;
116   ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
117   void AdjustSpillMask() OVERRIDE;
118   void ClobberCallerSave() OVERRIDE;
119   void FreeCallTemps() OVERRIDE;
120   void LockCallTemps() OVERRIDE;
121   void CompilerInitializeRegAlloc() OVERRIDE;
122 
123   // Required for target - miscellaneous.
124   void AssembleLIR() OVERRIDE;
125   void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
126   void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
127                                 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
128   const char* GetTargetInstFmt(int opcode) OVERRIDE;
129   const char* GetTargetInstName(int opcode) OVERRIDE;
130   std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE;
131   ResourceMask GetPCUseDefEncoding() const OVERRIDE;
132   uint64_t GetTargetInstFlags(int opcode) OVERRIDE;
133   size_t GetInsnSize(LIR* lir) OVERRIDE;
134   bool IsUnconditionalBranch(LIR* lir) OVERRIDE;
135 
136   // Get the register class for load/store of a field.
137   RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
138 
139   // Required for target - Dalvik-level generators.
140   void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
141                       RegLocation lr_shift) OVERRIDE;
142   void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
143                          RegLocation rl_src2) OVERRIDE;
144   void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
145                    RegLocation rl_dest, int scale) OVERRIDE;
146   void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
147                    RegLocation rl_src, int scale, bool card_mark) OVERRIDE;
148   void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
149                          RegLocation rl_shift) OVERRIDE;
150   void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
151                         RegLocation rl_src2) OVERRIDE;
152   void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
153                        RegLocation rl_src2) OVERRIDE;
154   void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
155                 RegLocation rl_src2) OVERRIDE;
156   void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
157   bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE;
158   bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE;
159   bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE;
160   bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE;
161   bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE;
162   bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE;
163   bool GenInlinedSqrt(CallInfo* info) OVERRIDE;
164   bool GenInlinedCeil(CallInfo* info) OVERRIDE;
165   bool GenInlinedFloor(CallInfo* info) OVERRIDE;
166   bool GenInlinedRint(CallInfo* info) OVERRIDE;
167   bool GenInlinedRound(CallInfo* info, bool is_double) OVERRIDE;
168   bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE;
169   bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE;
170   bool GenInlinedAbsLong(CallInfo* info) OVERRIDE;
171   bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE;
172   void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
173   void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
174                       RegLocation rl_src2) OVERRIDE;
175   RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div)
176       OVERRIDE;
177   RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div)
178       OVERRIDE;
179   void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)  OVERRIDE;
180   void GenDivZeroCheckWide(RegStorage reg) OVERRIDE;
181   void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE;
182   void GenExitSequence() OVERRIDE;
183   void GenSpecialExitSequence() OVERRIDE;
184   void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) OVERRIDE;
185   void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE;
186   void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE;
187   void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE;
188   void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
189                         int32_t true_val, int32_t false_val, RegStorage rs_dest,
190                         int dest_reg_class) OVERRIDE;
191 
192   bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE;
193   void GenMonitorEnter(int opt_flags, RegLocation rl_src) OVERRIDE;
194   void GenMonitorExit(int opt_flags, RegLocation rl_src) OVERRIDE;
195   void GenMoveException(RegLocation rl_dest) OVERRIDE;
196   void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
197                                      int first_bit, int second_bit) OVERRIDE;
198   void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
199   void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE;
200   void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
201   void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE;
202 
203   // Required for target - single operation generators.
204   LIR* OpUnconditionalBranch(LIR* target) OVERRIDE;
205   LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
206   LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
207   LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
208   LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
209   LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
210   LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
211   void OpEndIT(LIR* it) OVERRIDE;
212   LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
213   LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE;
214   LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
215   void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE;
216   LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE;
217   LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
218   LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
219   LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
220   LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
221   LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
222   LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
223   LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
224   LIR* OpTestSuspend(LIR* target) OVERRIDE;
225   LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
226   LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
227   void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE;
228 
229   bool InexpensiveConstantInt(int32_t value) OVERRIDE;
230   bool InexpensiveConstantInt(int32_t value, Instruction::Code opcode) OVERRIDE;
231   bool InexpensiveConstantFloat(int32_t value) OVERRIDE;
232   bool InexpensiveConstantLong(int64_t value) OVERRIDE;
233   bool InexpensiveConstantDouble(int64_t value) OVERRIDE;
234 
235   void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE;
236 
237   int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel,
238                            NextCallInsn next_call_insn,
239                            const MethodReference& target_method,
240                            uint32_t vtable_idx,
241                            uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
242                            bool skip_this) OVERRIDE;
243 
244   int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel,
245                          NextCallInsn next_call_insn,
246                          const MethodReference& target_method,
247                          uint32_t vtable_idx,
248                          uintptr_t direct_code, uintptr_t direct_method, InvokeType type,
249                          bool skip_this) OVERRIDE;
250 
WideGPRsAreAliases()251   bool WideGPRsAreAliases() OVERRIDE {
252     return true;  // 64b architecture.
253   }
WideFPRsAreAliases()254   bool WideFPRsAreAliases() OVERRIDE {
255     return true;  // 64b architecture.
256   }
257 
258   size_t GetInstructionOffset(LIR* lir) OVERRIDE;
259 
260   LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
261 
262  private:
263   /**
264    * @brief Given register xNN (dNN), returns register wNN (sNN).
265    * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2).
266    * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2).
267    * @see As64BitReg
268    */
As32BitReg(RegStorage reg)269   RegStorage As32BitReg(RegStorage reg) {
270     DCHECK(!reg.IsPair());
271     if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) {
272       if (kFailOnSizeError) {
273         LOG(FATAL) << "Expected 64b register";
274       } else {
275         LOG(WARNING) << "Expected 64b register";
276         return reg;
277       }
278     }
279     RegStorage ret_val = RegStorage(RegStorage::k32BitSolo,
280                                     reg.GetRawBits() & RegStorage::kRegTypeMask);
281     DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask)
282               ->GetReg().GetReg(),
283               ret_val.GetReg());
284     return ret_val;
285   }
286 
Check32BitReg(RegStorage reg)287   RegStorage Check32BitReg(RegStorage reg) {
288     if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) {
289       if (kFailOnSizeError) {
290         LOG(FATAL) << "Checked for 32b register";
291       } else {
292         LOG(WARNING) << "Checked for 32b register";
293         return As32BitReg(reg);
294       }
295     }
296     return reg;
297   }
298 
299   /**
300    * @brief Given register wNN (sNN), returns register xNN (dNN).
301    * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2).
302    * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2).
303    * @see As32BitReg
304    */
As64BitReg(RegStorage reg)305   RegStorage As64BitReg(RegStorage reg) {
306     DCHECK(!reg.IsPair());
307     if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) {
308       if (kFailOnSizeError) {
309         LOG(FATAL) << "Expected 32b register";
310       } else {
311         LOG(WARNING) << "Expected 32b register";
312         return reg;
313       }
314     }
315     RegStorage ret_val = RegStorage(RegStorage::k64BitSolo,
316                                     reg.GetRawBits() & RegStorage::kRegTypeMask);
317     DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask)
318               ->GetReg().GetReg(),
319               ret_val.GetReg());
320     return ret_val;
321   }
322 
Check64BitReg(RegStorage reg)323   RegStorage Check64BitReg(RegStorage reg) {
324     if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) {
325       if (kFailOnSizeError) {
326         LOG(FATAL) << "Checked for 64b register";
327       } else {
328         LOG(WARNING) << "Checked for 64b register";
329         return As64BitReg(reg);
330       }
331     }
332     return reg;
333   }
334 
335   int32_t EncodeImmSingle(uint32_t bits);
336   int32_t EncodeImmDouble(uint64_t bits);
337   LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value);
338   LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value);
339   void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
340   void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
341   void AssignDataOffsets();
342   RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
343                         bool is_div, bool check_zero);
344   RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
345   size_t GetLoadStoreSize(LIR* lir);
346 
347   bool SmallLiteralDivRem64(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
348                             RegLocation rl_dest, int64_t lit);
349 
350   uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
351   int AssignInsnOffsets();
352   void AssignOffsets();
353   uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
354 
355   // Spill core and FP registers. Returns the SP difference: either spill size, or whole
356   // frame size.
357   int SpillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size);
358 
359   // Unspill core and FP registers.
360   void UnspillRegs(RegStorage base, uint32_t core_reg_mask, uint32_t fp_reg_mask, int frame_size);
361 
362   void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
363 
364   LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value);
365   LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value);
366 
367   LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
368   LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
369                         int shift);
370   int EncodeShift(int code, int amount);
371 
372   LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2,
373                       A64RegExtEncodings ext, uint8_t amount);
374   LIR* OpRegRegRegExtend(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
375                          A64RegExtEncodings ext, uint8_t amount);
376   int EncodeExtend(int extend_type, int amount);
377   bool IsExtendEncoding(int encoded_value);
378 
379   LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
380   LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
381 
382   int EncodeLogicalImmediate(bool is_wide, uint64_t value);
383   uint64_t DecodeLogicalImmediate(bool is_wide, int value);
384   ArmConditionCode ArmConditionEncoding(ConditionCode code);
385 
386   // Helper used in the two GenSelect variants.
387   void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
388                  int result_reg_class);
389 
390   void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
391   void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
392   void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
393                      RegLocation rl_src2, bool is_div);
394 
395   InToRegStorageMapping in_to_reg_storage_mapping_;
396   static const ArmEncodingMap EncodingMap[kA64Last];
397 };
398 
399 }  // namespace art
400 
401 #endif  // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_
402