| /art/compiler/dex/quick/arm64/ |
| D | target_arm64.cc | 235 static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { in DecodeRegExtendOrShift() argument
236 if ((operand & (1 << 6)) == 0) { in DecodeRegExtendOrShift()
237 const char *shift_name = shift_names[(operand >> 7) & 0x3]; in DecodeRegExtendOrShift()
238 int amount = operand & 0x3f; in DecodeRegExtendOrShift()
241 const char *extend_name = extend_names[(operand >> 3) & 0x7]; in DecodeRegExtendOrShift()
242 int amount = operand & 0x7; in DecodeRegExtendOrShift()
342 int operand; in BuildInsnString() local
352 operand = lir->operands[nc-'0']; in BuildInsnString()
359 if (LIKELY(operand == omittable)) { in BuildInsnString()
362 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); in BuildInsnString()
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| D | assemble_arm64.cc | 670 uint32_t operand = lir->operands[i]; in EncodeLIRs() local
677 bool is_zero = A64_REG_IS_ZR(operand); in EncodeLIRs()
726 RegStorage reg(operand | RegStorage::kValid); in EncodeLIRs()
751 << ". Expected " << expected << ", got 0x" << std::hex << operand; in EncodeLIRs()
754 << ". Expected " << expected << ", got 0x" << std::hex << operand; in EncodeLIRs()
767 value = (operand << encoder->field_loc[i].start) & in EncodeLIRs()
780 DCHECK_EQ((operand & (1 << 6)) == 0, kind == kFmtShift); in EncodeLIRs()
781 value = (operand & 0x3f) << 10; in EncodeLIRs()
782 value |= ((operand & 0x1c0) >> 6) << 21; in EncodeLIRs()
786 value = (operand & 0x3) << 29; in EncodeLIRs()
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| /art/compiler/dex/quick/arm/ |
| D | target_arm.cc | 361 int operand; in BuildInsnString() local
371 operand = lir->operands[nc-'0']; in BuildInsnString()
374 if (operand != 0) { in BuildInsnString()
375 snprintf(tbuf, arraysize(tbuf), ", %s %d", shift_names[operand & 0x3], operand >> 2); in BuildInsnString()
381 switch (operand) { in BuildInsnString()
409 tbuf[i] += operand & 1; in BuildInsnString()
410 operand >>= 1; in BuildInsnString()
414 operand = ~ExpandImmediate(operand); in BuildInsnString()
415 snprintf(tbuf, arraysize(tbuf), "%d [%#x]", operand, operand); in BuildInsnString()
418 operand = ExpandImmediate(operand); in BuildInsnString()
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| D | assemble_arm.cc | 1087 uint32_t operand; in EncodeLIRs() local
1089 operand = lir->operands[i]; in EncodeLIRs()
1092 value = (operand << encoder->field_loc[i].start) & in EncodeLIRs()
1103 value = ((operand & 0xF0) >> 4) << encoder->field_loc[i].end; in EncodeLIRs()
1104 value |= (operand & 0x0F) << encoder->field_loc[i].start; in EncodeLIRs()
1108 value = ((operand & 0x80000) >> 19) << 26; in EncodeLIRs()
1109 value |= ((operand & 0x40000) >> 18) << 11; in EncodeLIRs()
1110 value |= ((operand & 0x20000) >> 17) << 13; in EncodeLIRs()
1111 value |= ((operand & 0x1f800) >> 11) << 16; in EncodeLIRs()
1112 value |= (operand & 0x007ff); in EncodeLIRs()
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| /art/compiler/dex/quick/mips/ |
| D | target_mips.cc | 201 int operand; in BuildInsnString() local
211 operand = lir->operands[nc-'0']; in BuildInsnString()
216 tbuf[i] += operand & 1; in BuildInsnString()
217 operand >>= 1; in BuildInsnString()
221 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); in BuildInsnString()
224 DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0); in BuildInsnString()
225 snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); in BuildInsnString()
228 snprintf(tbuf, arraysize(tbuf), "%04x", operand); in BuildInsnString()
232 snprintf(tbuf, arraysize(tbuf), "%d", operand); in BuildInsnString()
235 snprintf(tbuf, arraysize(tbuf), "%d", operand+1); in BuildInsnString()
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| D | assemble_mips.cc | 654 uint32_t operand; in AssembleInstructions() local
656 operand = lir->operands[i]; in AssembleInstructions()
662 value = operand; in AssembleInstructions()
664 value = (operand << encoder->field_loc[i].start) & in AssembleInstructions()
670 value = (operand & 0x1f); in AssembleInstructions()
676 DCHECK(RegStorage::IsDouble(operand)) << ", Operand = 0x" << std::hex << operand; in AssembleInstructions()
677 DCHECK_EQ((operand & 0x1), 0U); in AssembleInstructions()
678 value = (RegStorage::RegNum(operand) << encoder->field_loc[i].start) & in AssembleInstructions()
684 DCHECK(RegStorage::IsSingle(operand)) << ", Operand = 0x" << std::hex << operand; in AssembleInstructions()
685 value = (RegStorage::RegNum(operand) << encoder->field_loc[i].start) & in AssembleInstructions()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 440 void shll(CpuRegister operand, CpuRegister shifter);
442 void shrl(CpuRegister operand, CpuRegister shifter);
444 void sarl(CpuRegister operand, CpuRegister shifter);
626 void EmitOperand(uint8_t rm, const Operand& operand);
628 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate);
634 void EmitGenericShift(int rm, CpuRegister operand, CpuRegister shifter);
645 void EmitOptionalRex32(const Operand& operand);
646 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
647 void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
652 void EmitRex64(CpuRegister dst, const Operand& operand);
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| D | assembler_x86_64.cc | 1248 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { in shll() argument
1249 EmitGenericShift(4, operand, shifter); in shll()
1263 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { in shrl() argument
1264 EmitGenericShift(5, operand, shifter); in shrl()
1273 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { in sarl() argument
1274 EmitGenericShift(7, operand, shifter); in sarl()
1520 void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) { in EmitOperand() argument
1523 const int length = operand.length_; in EmitOperand()
1526 CHECK_EQ(operand.encoding_[0] & 0x38, 0); in EmitOperand()
1527 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3)); in EmitOperand()
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 1053 void X86Assembler::shll(Register operand, Register shifter) { in shll() argument
1054 EmitGenericShift(4, operand, shifter); in shll()
1063 void X86Assembler::shrl(Register operand, Register shifter) { in shrl() argument
1064 EmitGenericShift(5, operand, shifter); in shrl()
1073 void X86Assembler::sarl(Register operand, Register shifter) { in sarl() argument
1074 EmitGenericShift(7, operand, shifter); in sarl()
1324 void X86Assembler::EmitOperand(int reg_or_opcode, const Operand& operand) { in EmitOperand() argument
1327 const int length = operand.length_; in EmitOperand()
1330 CHECK_EQ(operand.encoding_[0] & 0x38, 0); in EmitOperand()
1331 EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3)); in EmitOperand()
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| D | assembler_x86.h | 400 void shll(Register operand, Register shifter);
402 void shrl(Register operand, Register shifter);
404 void sarl(Register operand, Register shifter);
582 void EmitOperand(int rm, const Operand& operand);
584 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate);
590 void EmitGenericShift(int rm, Register operand, Register shifter);
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| /art/compiler/dex/quick/x86/ |
| D | target_x86.cc | 352 int operand = lir->operands[operand_number]; in BuildInsnString() local
355 DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); in BuildInsnString()
356 buf += x86CondName[operand]; in BuildInsnString()
359 buf += StringPrintf("%d", operand); in BuildInsnString()
362 int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | in BuildInsnString()
367 EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); in BuildInsnString()
372 if (RegStorage::IsFloat(operand)) { in BuildInsnString()
373 int fp_reg = RegStorage::RegNum(operand); in BuildInsnString()
376 int reg_num = RegStorage::RegNum(operand); in BuildInsnString()
383 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, in BuildInsnString()
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| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 578 ShifterOperand operand; in VisitIf() local
579 if (ShifterOperand::CanHoldArm(value, &operand)) { in VisitIf()
617 ShifterOperand operand; in VisitCondition() local
618 if (ShifterOperand::CanHoldArm(value, &operand)) { in VisitCondition()
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