| /art/compiler/utils/x86_64/ |
| D | managed_register_x86_64.h | 190 explicit X86_64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} in X86_64ManagedRegister() argument
192 static X86_64ManagedRegister FromRegId(int reg_id) { in FromRegId() argument
193 X86_64ManagedRegister reg(reg_id); in FromRegId()
|
| /art/compiler/utils/x86/ |
| D | managed_register_x86.h | 204 explicit X86ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} in X86ManagedRegister() argument
206 static X86ManagedRegister FromRegId(int reg_id) { in FromRegId() argument
207 X86ManagedRegister reg(reg_id); in FromRegId()
|
| /art/compiler/utils/mips/ |
| D | managed_register_mips.h | 207 explicit MipsManagedRegister(int reg_id) : ManagedRegister(reg_id) {} in MipsManagedRegister() argument
209 static MipsManagedRegister FromRegId(int reg_id) { in FromRegId() argument
210 MipsManagedRegister reg(reg_id); in FromRegId()
|
| /art/compiler/utils/arm64/ |
| D | managed_register_arm64.h | 207 explicit Arm64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} in Arm64ManagedRegister() argument
209 static Arm64ManagedRegister FromRegId(int reg_id) { in FromRegId() argument
210 Arm64ManagedRegister reg(reg_id); in FromRegId()
|
| /art/compiler/dex/quick/ |
| D | local_optimizations.cc | 92 inline void Mir2Lir::EliminateLoad(LIR* lir, int reg_id) { in EliminateLoad() argument
93 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id)); in EliminateLoad()
97 if (lir->operands[0] == reg_id) { in EliminateLoad()
103 switch (reg_id & RegStorage::kShapeTypeMask) { in EliminateLoad()
106 src_reg = RegStorage::Solo32(reg_id); in EliminateLoad()
110 src_reg = RegStorage::Solo64(reg_id); in EliminateLoad()
114 src_reg = RegStorage::FloatSolo32(reg_id); in EliminateLoad()
118 src_reg = RegStorage::FloatSolo64(reg_id); in EliminateLoad()
|
| D | codegen_util.cc | 171 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, in AnnotateDalvikRegAccess() argument
180 lir->flags.alias_info = ENCODE_ALIAS_INFO(reg_id, is64bit); in AnnotateDalvikRegAccess()
|
| D | mir_to_lir.h | 668 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
672 void EliminateLoad(LIR* lir, int reg_id);
|
| /art/compiler/utils/arm/ |
| D | managed_register_arm.h | 253 explicit ArmManagedRegister(int reg_id) : ManagedRegister(reg_id) {} in ArmManagedRegister() argument
255 static ArmManagedRegister FromRegId(int reg_id) { in FromRegId() argument
256 ArmManagedRegister reg(reg_id); in FromRegId()
|
| /art/compiler/utils/ |
| D | managed_register.h | 74 explicit ManagedRegister(int reg_id) : id_(reg_id) { } in ManagedRegister() argument
|
| /art/compiler/dex/quick/arm/ |
| D | target_arm.cc | 303 int reg_id = i; in DecodeRegList() local
305 reg_id = rs_rARM_LR.GetRegNum(); in DecodeRegList()
307 reg_id = rs_rARM_PC.GetRegNum(); in DecodeRegList()
310 snprintf(buf + strlen(buf), buf_size - strlen(buf), ", r%d", reg_id); in DecodeRegList()
313 snprintf(buf, buf_size, "r%d", reg_id); in DecodeRegList()
|
| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 991 int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; in GenInlinedCas() local
992 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
998 int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; in GenInlinedCas() local
999 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
|
| D | target_x86.cc | 1364 int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - 1; in GenInlinedIndexOf() local
1365 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedIndexOf()
|