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Searched refs:right (Results 1 – 9 of 9) sorted by relevance

/art/compiler/sea_ir/code_gen/
Dcode_gen.cc152 llvm::Value* right = llvm_data_->GetValue(use_r); in Visit() local
153 llvm::Value* ifne = llvm_data_->builder_.CreateICmpNE(left, right, instruction->StringId()); in Visit()
190 llvm::Value* right = llvm::ConstantInt::get(*llvm_data_->context_, llvm::APInt(32, 0)); in Visit() local
191 llvm::Value* result = llvm_data_->builder_.CreateAdd(left, right); in Visit()
226 llvm::Value* right = llvm_data_->GetValue(use_r); in Visit() local
227 llvm::Value* result = llvm_data_->builder_.CreateAdd(left, right); in Visit()
/art/runtime/verifier/
Dreg_type_cache.cc316 RegType& RegTypeCache::FromUnresolvedMerge(RegType& left, RegType& right) { in FromUnresolvedMerge() argument
323 if (right.IsUnresolvedMergedReference()) { in FromUnresolvedMerge()
324 std::set<uint16_t> right_types = (down_cast<UnresolvedMergedType*>(&right))->GetMergedTypes(); in FromUnresolvedMerge()
327 types.insert(right.GetId()); in FromUnresolvedMerge()
341 RegType* entry = new UnresolvedMergedType(left.GetId(), right.GetId(), this, entries_.size()); in FromUnresolvedMerge()
Dreg_type_cache.h67 RegType& FromUnresolvedMerge(RegType& left, RegType& right)
Dreg_type.cc595 UnresolvedMergedType* right = down_cast<UnresolvedMergedType*>(&_right); in GetMergedTypes() local
603 if (right->IsUnresolvedMergedReference()) { in GetMergedTypes()
604 std::set<uint16_t> right_types = right->GetMergedTypes(); in GetMergedTypes()
/art/compiler/optimizing/
Dcode_generator_x86.cc1019 Location right = locations->InAt(1); in VisitCompare() local
1020 if (right.IsRegister()) { in VisitCompare()
1021 __ cmpl(left.AsRegisterPairHigh(), right.AsX86().AsRegisterPairHigh()); in VisitCompare()
1023 DCHECK(right.IsDoubleStackSlot()); in VisitCompare()
1024 __ cmpl(left.AsRegisterPairHigh(), Address(ESP, right.GetHighStackIndex(kX86WordSize))); in VisitCompare()
1028 if (right.IsRegister()) { in VisitCompare()
1029 __ cmpl(left.AsRegisterPairLow(), right.AsX86().AsRegisterPairLow()); in VisitCompare()
1031 DCHECK(right.IsDoubleStackSlot()); in VisitCompare()
1032 __ cmpl(left.AsRegisterPairLow(), Address(ESP, right.GetStackIndex())); in VisitCompare()
Dnodes.h901 HInstruction* right) : HExpression(result_type) { in HBinaryOperation() argument
903 SetRawInputAt(1, right); in HBinaryOperation()
1210 HAdd(Primitive::Type result_type, HInstruction* left, HInstruction* right) in HAdd() argument
1211 : HBinaryOperation(result_type, left, right) {} in HAdd()
1223 HSub(Primitive::Type result_type, HInstruction* left, HInstruction* right) in HSub() argument
1224 : HBinaryOperation(result_type, left, right) {} in HSub()
Dcode_generator_arm.cc1054 ArmManagedRegister right = locations->InAt(1).AsArm(); in VisitCompare() local
1057 ShifterOperand(right.AsRegisterPairHigh())); // Signed compare. in VisitCompare()
1064 ShifterOperand(right.AsRegisterPairLow())); // Unsigned compare. in VisitCompare()
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h387 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
/art/runtime/arch/mips/
Dquick_entrypoints_mips.S499 srl $t0, $t0, 4 # shift the frame size right 4