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Searched refs:rs_src1 (Results 1 – 2 of 2) sorted by relevance

/art/compiler/dex/quick/x86/
Dtarget_x86.cc2124 void X86Mir2Lir::AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, u… in AndMaskVectorRegister() argument
2125 MaskVectorRegister(kX86PandRM, rs_src1, m1, m2, m3, m4); in AndMaskVectorRegister()
2128 void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1,… in MaskVectorRegister() argument
2139 AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp); in MaskVectorRegister()
2144 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenAddReduceVector() local
2176 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); in GenAddReduceVector()
2177 NewLIR3(kX86ShufpsRRI, rs_src1.GetReg(), rs_src1.GetReg(), 0x39); in GenAddReduceVector()
2179 NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), rs_src1.GetReg()); in GenAddReduceVector()
2197 NewLIR2(kX86Mova128RR, rs_tmp.GetReg(), rs_src1.GetReg()); in GenAddReduceVector()
2201 AndMaskVectorRegister(rs_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); in GenAddReduceVector()
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Dcodegen_x86.h484 …void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4);
485 …void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m…