1# Sample variables file for BCM94356 WLBGA iPA, eLNA+switch board with PCIe for production package
2# History:
3#      1. July 24 2014 - updated pa parameters by BRCM
4#      2. August 22 2014 - updated pa parameters by MOTO (John Ballen)
5#      3. September 19 2014 - use GPIO instead of PCIe to wake up the host (Andrey Gostev)
6# Following fields WILL be written into OTP
7
8# Following fields WILL NOT be written in OTP
9# [NVRAM ONLY]
10NVRAMRev=$Rev: 373428 $
11sromrev=11
12boardrev=0x1101
13macaddr=00:90:4c:19:80:01
14boardtype=0x0732
15boardflags=0x12401201
16#enable LNA1 bypass for both 2G & 5G
17boardflags2=0x00802000
18boardflags3=0x4800018a
19#boardnum=57410
20ccode=0
21regrev=0
22antswitch=0
23pdgain5g=4
24pdgain2g=4
25tworangetssi2g=0
26tworangetssi5g=0
27paprdis=0
28femctrl=10
29vendid=0x14e4
30devid=0x43ec
31manfid=0x2d0
32#prodid=0x052e
33nocrc=1
34otpimagesize=484
35xtalfreq=37400
36rxgains2gtrelnabypa0=1
37rxgains2gtrelnabypa1=1
38#2G elna gain from datasheet is 14dB
39#2G elna gain changed to 12dB
40rxgains2gelnagaina0=3
41rxgains2gelnagaina1=3
42#triso values for 2G are picked from older nvram. Might need to change.
43rxgains2gtrisoa0=6
44rxgains2gtrisoa1=6
45rxgains5gtrelnabypa0=1
46rxgains5gmtrelnabypa0=1
47rxgains5ghtrelnabypa0=1
48rxgains5gtrelnabypa1=1
49rxgains5gmtrelnabypa1=1
50rxgains5ghtrelnabypa1=1
51#5G elna gain from datasheet is 12dB
52rxgains5gelnagaina0=3
53rxgains5gmelnagaina0=3
54rxgains5ghelnagaina0=3
55rxgains5gelnagaina1=3
56rxgains5gmelnagaina1=3
57rxgains5ghelnagaina1=3
58#triso values for 5G are picked from older nvram. Might need to change.
59rxgains5gtrisoa0=5
60rxgains5gmtrisoa0=6
61rxgains5ghtrisoa0=6
62rxgains5gtrisoa1=5
63rxgains5gmtrisoa1=6
64rxgains5ghtrisoa1=6
65rxchain=3
66txchain=3
67aa2g=3
68aa5g=3
69agbg0=2
70agbg1=2
71aga0=2
72aga1=2
73tssipos2g=1
74extpagain2g=2
75tssipos5g=1
76extpagain5g=2
77tempthresh=120
78tempoffset=255
79rawtempsense=0x1ff
80pa2ga0=-152,5791,-672
81pa2ga1=-135,6043,-685
82pa2gccka0=-167,6004,-717
83pa2gccka1=-171,6024,-725
84pa5ga0=-228,5211,-665,-229,5136,-656,-219,5440,-690,-225,5321,-677
85pa5ga1=-190,6045,-742,-172,6243,-743,-204,5889,-726,-208,5853,-727
86subband5gver=0x4
87pdoffsetcckma0=0x3333
88pdoffsetcckma1=0x3333
89pdoffset40ma0=0x0000
90pdoffset80ma0=0x0000
91pdoffset40ma1=0x0000
92pdoffset80ma1=0x0000
93maxp2ga0=74
94maxp5ga0=74,74,74,74
95maxp2ga1=74
96maxp5ga1=74,74,74,74
97cckbw202gpo=0x0000
98cckbw20ul2gpo=0x0000
99mcsbw202gpo=0xa9855422
100mcsbw402gpo=0xa9855422
101dot11agofdmhrbw202gpo=0x5542
102ofdmlrbw202gpo=0x0022
103mcsbw205glpo=0xa9866663
104mcsbw405glpo=0xb9966664
105mcsbw805glpo=0xbb866665
106mcsbw205gmpo=0xd9866663
107mcsbw405gmpo=0xa9866663
108mcsbw805gmpo=0xcc866665
109mcsbw205ghpo=0xdc866663
110mcsbw405ghpo=0xaa866663
111mcsbw805ghpo=0xdd866665
112mcslr5glpo=0x0000
113mcslr5gmpo=0x0000
114mcslr5ghpo=0x0000
115sb20in40hrpo=0x0
116sb20in80and160hr5glpo=0x0
117sb40and80hr5glpo=0x0
118sb20in80and160hr5gmpo=0x0
119sb40and80hr5gmpo=0x0
120sb20in80and160hr5ghpo=0x0
121sb40and80hr5ghpo=0x0
122sb20in40lrpo=0x0
123sb20in80and160lr5glpo=0x0
124sb40and80lr5glpo=0x0
125sb20in80and160lr5gmpo=0x0
126sb40and80lr5gmpo=0x0
127sb20in80and160lr5ghpo=0x0
128sb40and80lr5ghpo=0x0
129dot11agduphrpo=0x0
130dot11agduplrpo=0x0
131phycal_tempdelta=25
132temps_period=15
133temps_hysteresis=15
134AvVmid_c0=2,140,2,145,2,145,2,145,2,145
135AvVmid_c1=2,140,2,145,2,145,2,145,2,145
136AvVmid_c2=0,0,0,0,0,0,0,0,0,0
137rssicorrnorm_c0=4,4
138rssicorrnorm_c1=4,4
139rssicorrnorm5g_c0=1,2,3,1,2,3,1,2,3,1,2,3
140rssicorrnorm5g_c1=1,2,3,1,2,3,1,2,3,1,2,3
141epsdelta2g0=0
142epsdelta2g1=0
143ofdmfilttype=1
144swctrlmap_2g=0x00001040,0xC0300000,0x40200000,0x803020,0x0ff
145swctrlmap_5g=0x00000202,0x05050000,0x01010000,0x000000,0x047
146swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000
147swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000
148ltecxmux=0x534201
149btc_mode=1
150cckdigfilttype=1
151cck_onecore_tx = 1
152host_wake_opt=0
153phy4350_ss_opt=1
154#PCIe Header Values
155#pciehdr_00=0x380f
156#pciehdr_01=0x3800
157#pciehdr_02=${boardtype}
158#pciehdr_03=${vendid}
159#pciehdr_04=0x021c
160#pciehdr_05=0x1b7e
161#pciehdr_06=0x0a00
162#pciehdr_07=0x0000
163#pciehdr_08=0x0000
164#pciehdr_09=0x0000
165#pciehdr_10=0x0000
166#pciehdr_11=0x0000
167#pciehdr_12=0x00d4
168#pciehdr_13=0x253c
169#pciehdr_14=0x2164
170#pciehdr_15=0x3203
171#pciehdr_16=0x3e5f
172#pciehdr_17=0x9605
173#pciehdr_18=0x9f2f
174#pciehdr_19=0x79b6
175#pciehdr_20=0x8080
176#pciehdr_21=0x0c03
177#pciehdr_22=0x4000
178#pciehdr_23=0x3240
179#pciehdr_24=0x5f00
180#pciehdr_25=0x4df4
181#pciehdr_26=0x8090
182#pciehdr_27=0xee00
183#pciehdr_28=0x8630
184#pciehdr_29=0x0180
185#pciehdr_30=0x002b
186#pciehdr_31=0x0000
187#pciehdr_32=0x0000
188#pciehdr_33=0x0000
189#pciehdr_34=0x0000
190#pciehdr_35=0x0000
191#pciehdr_36=0x0000
192#pciehdr_37=0x0000
193#pciehdr_38=0x0000
194#pciehdr_39=0x0000
195#pciehdr_40=0x0000
196#pciehdr_41=0x0000
197#pciehdr_42=0x8800
198#pciehdr_43=0x030a
199#pciehdr_44=0x0160
200#pciehdr_45=0x0000
201#pciehdr_46=0x0000
202#pciehdr_47=0x0000
203#pciehdr_48=${devid}
204#pciehdr_49=0x8000
205#pciehdr_50=0x0002
206#pciehdr_51=0x0000
207#pciehdr_52=0x3ff5
208#pciehdr_53=0x1800
209#pciehdr_54=0x0000
210#pciehdr_55=0x0000
211#pciehdr_56=0x0000
212#pciehdr_57=0x0000
213#pciehdr_58=0x0000
214#pciehdr_59=0x0000
215#pciehdr_60=0x0000
216#pciehdr_61=0x0000
217#pciehdr_62=0x0000
218#pciehdr_63=0x0000
219