32 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {  in OpFpRegCopy()
101 bool MipsMir2Lir::InexpensiveConstantInt(int32_t value) {  in InexpensiveConstantInt()
106 bool MipsMir2Lir::InexpensiveConstantFloat(int32_t value) {  in InexpensiveConstantFloat()
111 bool MipsMir2Lir::InexpensiveConstantLong(int64_t value) {  in InexpensiveConstantLong()
116 bool MipsMir2Lir::InexpensiveConstantDouble(int64_t value) {  in InexpensiveConstantDouble()
130 LIR* MipsMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {  in LoadConstantNoClobber()
163 LIR* MipsMir2Lir::LoadConstantWideNoClobber(RegStorage r_dest, int64_t value) {  in LoadConstantWideNoClobber()
274 LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) {  in OpUnconditionalBranch()
280 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {  in OpReg()
295 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {  in OpRegImm()
304 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) {  in OpRegRegReg()
346 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) {  in OpRegRegImm()
466 LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {  in OpRegReg()
523 LIR* MipsMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset,  in OpMovRegMem()
530 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {  in OpMovMemReg()
536 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {  in OpCondRegReg()
542 LIR* MipsMir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {  in LoadConstantWide()
569 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,  in LoadBaseIndexed()
643 LIR* MipsMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,  in StoreBaseIndexed()
690 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,  in LoadBaseDispBody()
835 void MipsMir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags, bool is_wide) {  in ForceImplicitNullCheck()
851 LIR* MipsMir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,  in LoadBaseDisp()
875 LIR* MipsMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,  in StoreBaseDispBody()
1004 LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,  in StoreBaseDisp()
1034 LIR* MipsMir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {  in OpMem()
1040 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {  in OpCondBranch()
1046 LIR* MipsMir2Lir::InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) {  in InvokeTrampoline()
1062 RegStorage MipsMir2Lir::AllocPtrSizeTemp(bool required) {  in AllocPtrSizeTemp()