32 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {  in OpFpRegCopy()  argument
35     DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit());  in OpFpRegCopy()
38         if (r_src.IsDouble()) {  in OpFpRegCopy()
42           RegStorage t_opnd = r_src;  in OpFpRegCopy()
43           r_src = r_dest;  in OpFpRegCopy()
48         DCHECK(r_src.IsDouble());  in OpFpRegCopy()
53         if (r_src.IsSingle()) {  in OpFpRegCopy()
57           RegStorage t_opnd = r_src;  in OpFpRegCopy()
58           r_src = r_dest;  in OpFpRegCopy()
63         DCHECK(r_src.IsSingle());  in OpFpRegCopy()
69     DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());  in OpFpRegCopy()
74         if (r_src.IsSingle()) {  in OpFpRegCopy()
78           RegStorage t_opnd = r_src;  in OpFpRegCopy()
79           r_src = r_dest;  in OpFpRegCopy()
84         DCHECK(r_src.IsSingle());  in OpFpRegCopy()
91     res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());  in OpFpRegCopy()
93     res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg());  in OpFpRegCopy()
95   if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) {  in OpFpRegCopy()
530 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {  in OpMovMemReg()  argument
531   UNUSED(r_base, offset, r_src, move_type);  in OpMovMemReg()
536 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {  in OpCondRegReg()  argument
537   UNUSED(op, cc, r_dest, r_src);  in OpCondRegReg()
643 LIR* MipsMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,  in StoreBaseIndexed()  argument
649   if (r_src.IsFloat()) {  in StoreBaseIndexed()
650     DCHECK(r_src.IsSingle());  in StoreBaseIndexed()
685   NewLIR3(opcode, r_src.GetReg(), 0, t_reg.GetReg());  in StoreBaseIndexed()
875 LIR* MipsMir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,  in StoreBaseDispBody()  argument
888         r_src = Check64BitReg(r_src);  in StoreBaseDispBody()
889         if (!r_src.IsFloat()) {  in StoreBaseDispBody()
898       if (fpuIs32Bit_ && !r_src.IsPair()) {  in StoreBaseDispBody()
900         r_src = Solo64ToPair64(r_src);  in StoreBaseDispBody()
908       if (r_src.IsFloat()) {  in StoreBaseDispBody()
911           DCHECK(r_src.IsSingle());  in StoreBaseDispBody()
913           DCHECK(r_src.IsDouble());  in StoreBaseDispBody()
933       store = res = NewLIR3(opcode, r_src.GetReg(), displacement, r_base.GetReg());  in StoreBaseDispBody()
937       store = NewLIR3(opcode, r_src.GetReg(), 0, r_scratch.GetReg());  in StoreBaseDispBody()
943       AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit());  in StoreBaseDispBody()
950       store = res = NewLIR3(opcode, r_src.GetReg(), displacement, r_base.GetReg());  in StoreBaseDispBody()
952       if (fpuIs32Bit_ || !r_src.IsFloat()) {  in StoreBaseDispBody()
953         DCHECK(r_src.IsPair());  in StoreBaseDispBody()
954         store = res = NewLIR3(opcode, r_src.GetLowReg(), displacement + LOWORD_OFFSET,  in StoreBaseDispBody()
956         store2 = NewLIR3(opcode, r_src.GetHighReg(), displacement + HIWORD_OFFSET, r_base.GetReg());  in StoreBaseDispBody()
960         r_src = Fp64ToSolo32(r_src);  in StoreBaseDispBody()
961         store = res = NewLIR3(kMipsFswc1, r_src.GetReg(), displacement + LOWORD_OFFSET,  in StoreBaseDispBody()
963         NewLIR2(kMipsMfhc1, r_tmp.GetReg(), r_src.GetReg());  in StoreBaseDispBody()
972       store =  NewLIR3(opcode, r_src.GetReg(), 0, r_scratch.GetReg());  in StoreBaseDispBody()
974       if (fpuIs32Bit_ || !r_src.IsFloat()) {  in StoreBaseDispBody()
975         DCHECK(r_src.IsPair());  in StoreBaseDispBody()
976         store = NewLIR3(opcode, r_src.GetLowReg(), LOWORD_OFFSET, r_scratch.GetReg());  in StoreBaseDispBody()
977         store2 = NewLIR3(opcode, r_src.GetHighReg(), HIWORD_OFFSET, r_scratch.GetReg());  in StoreBaseDispBody()
981         r_src = Fp64ToSolo32(r_src);  in StoreBaseDispBody()
982         store = NewLIR3(kMipsFswc1, r_src.GetReg(), LOWORD_OFFSET, r_scratch.GetReg());  in StoreBaseDispBody()
983         NewLIR2(kMipsMfhc1, r_tmp.GetReg(), r_src.GetReg());  in StoreBaseDispBody()
1004 LIR* MipsMir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,  in StoreBaseDisp()  argument
1016     store = GenAtomic64Store(r_base, displacement, r_src);  in StoreBaseDisp()
1022     store = StoreBaseDispBody(r_base, displacement, r_src, size);  in StoreBaseDisp()