Lines Matching refs:shift_imm
1153 void Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm, in Lsl() argument
1155 CHECK_LE(shift_imm, 31u); in Lsl()
1157 movs(rd, ShifterOperand(rm, LSL, shift_imm), cond); in Lsl()
1159 mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); in Lsl()
1164 void Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm, in Lsr() argument
1166 CHECK(1u <= shift_imm && shift_imm <= 32u); in Lsr()
1167 if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. in Lsr()
1169 movs(rd, ShifterOperand(rm, LSR, shift_imm), cond); in Lsr()
1171 mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); in Lsr()
1176 void Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm, in Asr() argument
1178 CHECK(1u <= shift_imm && shift_imm <= 32u); in Asr()
1179 if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. in Asr()
1181 movs(rd, ShifterOperand(rm, ASR, shift_imm), cond); in Asr()
1183 mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); in Asr()
1188 void Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm, in Ror() argument
1190 CHECK(1u <= shift_imm && shift_imm <= 31u); in Ror()
1192 movs(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()
1194 mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()