Lines Matching refs:so
59 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_() argument
61 EmitType01(cond, so.type(), AND, 0, rn, rd, so); in and_()
65 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor() argument
67 EmitType01(cond, so.type(), EOR, 0, rn, rd, so); in eor()
71 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub() argument
73 EmitType01(cond, so.type(), SUB, 0, rn, rd, so); in sub()
76 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb() argument
78 EmitType01(cond, so.type(), RSB, 0, rn, rd, so); in rsb()
81 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, in rsbs() argument
83 EmitType01(cond, so.type(), RSB, 1, rn, rd, so); in rsbs()
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add() argument
89 EmitType01(cond, so.type(), ADD, 0, rn, rd, so); in add()
93 void Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so, in adds() argument
95 EmitType01(cond, so.type(), ADD, 1, rn, rd, so); in adds()
99 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, in subs() argument
101 EmitType01(cond, so.type(), SUB, 1, rn, rd, so); in subs()
105 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so, in adc() argument
107 EmitType01(cond, so.type(), ADC, 0, rn, rd, so); in adc()
111 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so, in sbc() argument
113 EmitType01(cond, so.type(), SBC, 0, rn, rd, so); in sbc()
117 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so, in rsc() argument
119 EmitType01(cond, so.type(), RSC, 0, rn, rd, so); in rsc()
123 void Arm32Assembler::tst(Register rn, const ShifterOperand& so, Condition cond) { in tst() argument
125 EmitType01(cond, so.type(), TST, 1, rn, R0, so); in tst()
129 void Arm32Assembler::teq(Register rn, const ShifterOperand& so, Condition cond) { in teq() argument
131 EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); in teq()
135 void Arm32Assembler::cmp(Register rn, const ShifterOperand& so, Condition cond) { in cmp() argument
136 EmitType01(cond, so.type(), CMP, 1, rn, R0, so); in cmp()
140 void Arm32Assembler::cmn(Register rn, const ShifterOperand& so, Condition cond) { in cmn() argument
141 EmitType01(cond, so.type(), CMN, 1, rn, R0, so); in cmn()
146 const ShifterOperand& so, Condition cond) { in orr() argument
147 EmitType01(cond, so.type(), ORR, 0, rn, rd, so); in orr()
152 const ShifterOperand& so, Condition cond) { in orrs() argument
153 EmitType01(cond, so.type(), ORR, 1, rn, rd, so); in orrs()
157 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { in mov() argument
158 EmitType01(cond, so.type(), MOV, 0, R0, rd, so); in mov()
162 void Arm32Assembler::movs(Register rd, const ShifterOperand& so, Condition cond) { in movs() argument
163 EmitType01(cond, so.type(), MOV, 1, R0, rd, so); in movs()
167 void Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so, in bic() argument
169 EmitType01(cond, so.type(), BIC, 0, rn, rd, so); in bic()
173 void Arm32Assembler::mvn(Register rd, const ShifterOperand& so, Condition cond) { in mvn() argument
174 EmitType01(cond, so.type(), MVN, 0, R0, rd, so); in mvn()
178 void Arm32Assembler::mvns(Register rd, const ShifterOperand& so, Condition cond) { in mvns() argument
179 EmitType01(cond, so.type(), MVN, 1, R0, rd, so); in mvns()
589 const ShifterOperand& so) { in EmitType01() argument
598 so.encodingArm(); in EmitType01()
688 const ShifterOperand& so) { in EmitShiftImmediate() argument
690 CHECK(so.IsImmediate()); in EmitShiftImmediate()
694 so.encodingArm() << kShiftImmShift | in EmitShiftImmediate()
705 const ShifterOperand& so) { in EmitShiftRegister() argument
707 CHECK(so.IsRegister()); in EmitShiftRegister()
711 so.encodingArm() << kShiftRegisterShift | in EmitShiftRegister()