Lines Matching refs:ISD
199 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
201 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
228 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
260 case ISD::ADD: in LegalizeOp()
261 case ISD::SUB: in LegalizeOp()
262 case ISD::MUL: in LegalizeOp()
263 case ISD::SDIV: in LegalizeOp()
264 case ISD::UDIV: in LegalizeOp()
265 case ISD::SREM: in LegalizeOp()
266 case ISD::UREM: in LegalizeOp()
267 case ISD::FADD: in LegalizeOp()
268 case ISD::FSUB: in LegalizeOp()
269 case ISD::FMUL: in LegalizeOp()
270 case ISD::FDIV: in LegalizeOp()
271 case ISD::FREM: in LegalizeOp()
272 case ISD::AND: in LegalizeOp()
273 case ISD::OR: in LegalizeOp()
274 case ISD::XOR: in LegalizeOp()
275 case ISD::SHL: in LegalizeOp()
276 case ISD::SRA: in LegalizeOp()
277 case ISD::SRL: in LegalizeOp()
278 case ISD::ROTL: in LegalizeOp()
279 case ISD::ROTR: in LegalizeOp()
280 case ISD::BSWAP: in LegalizeOp()
281 case ISD::CTLZ: in LegalizeOp()
282 case ISD::CTTZ: in LegalizeOp()
283 case ISD::CTLZ_ZERO_UNDEF: in LegalizeOp()
284 case ISD::CTTZ_ZERO_UNDEF: in LegalizeOp()
285 case ISD::CTPOP: in LegalizeOp()
286 case ISD::SELECT: in LegalizeOp()
287 case ISD::VSELECT: in LegalizeOp()
288 case ISD::SELECT_CC: in LegalizeOp()
289 case ISD::SETCC: in LegalizeOp()
290 case ISD::ZERO_EXTEND: in LegalizeOp()
291 case ISD::ANY_EXTEND: in LegalizeOp()
292 case ISD::TRUNCATE: in LegalizeOp()
293 case ISD::SIGN_EXTEND: in LegalizeOp()
294 case ISD::FP_TO_SINT: in LegalizeOp()
295 case ISD::FP_TO_UINT: in LegalizeOp()
296 case ISD::FNEG: in LegalizeOp()
297 case ISD::FABS: in LegalizeOp()
298 case ISD::FMINNUM: in LegalizeOp()
299 case ISD::FMAXNUM: in LegalizeOp()
300 case ISD::FCOPYSIGN: in LegalizeOp()
301 case ISD::FSQRT: in LegalizeOp()
302 case ISD::FSIN: in LegalizeOp()
303 case ISD::FCOS: in LegalizeOp()
304 case ISD::FPOWI: in LegalizeOp()
305 case ISD::FPOW: in LegalizeOp()
306 case ISD::FLOG: in LegalizeOp()
307 case ISD::FLOG2: in LegalizeOp()
308 case ISD::FLOG10: in LegalizeOp()
309 case ISD::FEXP: in LegalizeOp()
310 case ISD::FEXP2: in LegalizeOp()
311 case ISD::FCEIL: in LegalizeOp()
312 case ISD::FTRUNC: in LegalizeOp()
313 case ISD::FRINT: in LegalizeOp()
314 case ISD::FNEARBYINT: in LegalizeOp()
315 case ISD::FROUND: in LegalizeOp()
316 case ISD::FFLOOR: in LegalizeOp()
317 case ISD::FP_ROUND: in LegalizeOp()
318 case ISD::FP_EXTEND: in LegalizeOp()
319 case ISD::FMA: in LegalizeOp()
320 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
321 case ISD::ANY_EXTEND_VECTOR_INREG: in LegalizeOp()
322 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
323 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
326 case ISD::FP_ROUND_INREG: in LegalizeOp()
329 case ISD::SINT_TO_FP: in LegalizeOp()
330 case ISD::UINT_TO_FP: in LegalizeOp()
370 case ISD::SINT_TO_FP: in Promote()
371 case ISD::UINT_TO_FP: in Promote()
374 case ISD::FP_TO_UINT: in Promote()
375 case ISD::FP_TO_SINT: in Promote()
377 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); in Promote()
399 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
401 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in Promote()
410 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0)); in Promote()
412 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
435 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : in PromoteINT_TO_FP()
436 ISD::SIGN_EXTEND; in PromoteINT_TO_FP()
461 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
462 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
465 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { in PromoteFP_TO_INT()
466 NewOpc = ISD::FP_TO_UINT; in PromoteFP_TO_INT()
473 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted); in PromoteFP_TO_INT()
483 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad()
528 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad()
538 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, in ExpandLoad()
558 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
559 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask); in ExpandLoad()
569 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
570 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask); in ExpandLoad()
575 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi); in ExpandLoad()
579 case ISD::EXTLOAD: in ExpandLoad()
582 case ISD::ZEXTLOAD: in ExpandLoad()
585 case ISD::SEXTLOAD: in ExpandLoad()
588 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
589 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
606 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, in ExpandLoad()
614 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in ExpandLoad()
615 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandLoad()
657 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in ExpandStore()
666 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, in ExpandStore()
671 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in ExpandStore()
678 case ISD::SIGN_EXTEND_INREG: in Expand()
680 case ISD::ANY_EXTEND_VECTOR_INREG: in Expand()
682 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
684 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
686 case ISD::BSWAP: in Expand()
688 case ISD::VSELECT: in Expand()
690 case ISD::SELECT: in Expand()
692 case ISD::UINT_TO_FP: in Expand()
694 case ISD::FNEG: in Expand()
696 case ISD::SETCC: in Expand()
724 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || in ExpandSELECT()
725 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || in ExpandSELECT()
726 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || in ExpandSELECT()
727 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) in ExpandSELECT()
742 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); in ExpandSELECT()
747 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
748 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
752 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); in ExpandSELECT()
754 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); in ExpandSELECT()
755 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
756 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
757 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); in ExpandSELECT()
764 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
765 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
776 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
777 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
801 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
821 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
822 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
841 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands); in ExpandZERO_EXTEND_VECTOR_INREG()
855 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
876 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0)); in ExpandBSWAP()
879 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
900 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || in ExpandVSELECT()
901 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || in ExpandVSELECT()
902 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || in ExpandVSELECT()
916 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT()
917 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
921 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); in ExpandVSELECT()
923 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); in ExpandVSELECT()
924 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
925 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
926 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); in ExpandVSELECT()
934 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
935 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
955 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
956 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask); in ExpandUINT_TO_FLOAT()
960 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
961 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
962 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
965 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); in ExpandUINT_TO_FLOAT()
970 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
972 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), in ExpandFNEG()
987 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
989 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
991 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
999 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in UnrollVSETCC()