116   bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
120                           unsigned RegA, unsigned RegB, unsigned Dist);
537 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {  in regsAreCompatible()  argument
538   if (RegA == RegB)  in regsAreCompatible()
540   if (!RegA || !RegB)  in regsAreCompatible()
542   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
668     unsigned RegA = MI->getOperand(0).getReg();  in commuteInstruction()  local
669     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
678 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){  in isProfitableToConv3Addr()  argument
688   unsigned ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
697                                               unsigned RegA, unsigned RegB,  in convertInstTo3Addr()  argument
728   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1431     unsigned RegA = DstMO.getReg();  in processTiedPairs()  local
1438     if (RegA == RegB) {  in processTiedPairs()
1445     LastCopiedReg = RegA;  in processTiedPairs()
1457              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1462                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1468       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1469         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1476         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1490       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1491         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1510     if (TargetRegisterInfo::isVirtualRegister(RegA) &&  in processTiedPairs()
1512       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1513     MO.setReg(RegA);  in processTiedPairs()
1520     SrcRegMap[RegA] = RegB;  in processTiedPairs()