Lines Matching refs:IntRegs
23 def I32 : PatLeaf<(i32 IntRegs:$R)>;
25 def F32 : PatLeaf<(f32 IntRegs:$R)>;
70 (ins IntRegs:$src1, ImmOp:$src2),
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>;
257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>;
300 def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
320 def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>;
351 : ALU32_ri <(outs IntRegs:$Rd),
352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
377 : ALU32_ri <(outs IntRegs:$Rd),
378 (ins IntRegs:$Rs, immOp:$s16),
429 : ALU32_ri <(outs IntRegs:$Rd),
430 (ins IntRegs:$Rs, s10Ext:$s10),
432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
455 def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
477 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
478 (A2_subri imm:$s10, IntRegs:$Rs)>;
481 def: Pat<(not (i32 IntRegs:$src1)),
482 (A2_subri -1, IntRegs:$src1)>;
486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
507 : ALU32Inst<(outs IntRegs:$dst),
508 (ins PredRegs:$src1, IntRegs:$src2),
530 class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
624 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
686 def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
690 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
702 def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
705 [(set (i32 IntRegs:$Rd),
734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
809 class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1124 def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
1188 (Inst IntRegs:$src1, IntRegs:$src2)>;
1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>;
1390 def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
1503 : JRInst<(outs), (ins IntRegs:$dst),
1515 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
1553 dag InputDag = (ins IntRegs:$Rs)>
1575 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1576 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
1609 def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
1610 (J2_jumpr IntRegs:$dst)>;
1611 def: Pat<(brind (i32 IntRegs:$dst)),
1612 (J2_jumpr IntRegs:$dst)>;
1626 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
1659 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1715 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
1716 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
1720 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
1721 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1725 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1731 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
1732 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1744 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1777 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
1778 (VT (MI IntRegs:$Rs, imm:$Off))>;
1779 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
1805 def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
1806 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
1817 : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
1818 (ins IntRegs:$src1, ImmOp:$offset),
1851 : LDInst <(outs RC:$dst, IntRegs:$dst2),
1852 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1909 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
1910 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
1915 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
1916 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
1921 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
1930 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
1931 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
1943 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
1944 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
1979 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
1980 (ins IntRegs:$src1, ModRegs:$src2),
2000 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
2001 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
2002 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
2003 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2004 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2006 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2016 (ins IntRegs:$addr, s11_2Ext:$off),
2033 : LDInst <(outs RC:$dst, IntRegs:$_dst_),
2034 (ins IntRegs:$Rz, ModRegs:$Mu),
2055 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
2056 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
2060 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
2061 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2062 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
2063 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2067 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2080 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
2081 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
2110 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
2111 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
2139 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
2140 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
2145 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
2146 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2147 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
2148 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
2153 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2173 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2174 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4),
2178 def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>;
2179 def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>;
2180 def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>;
2181 def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>;
2182 def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>;
2198 (ins IntRegs:$src),
2210 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
2217 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
2233 def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
2245 <(outs RC:$dst, IntRegs:$_dst_),
2246 (ins IntRegs:$Rz, ModRegs:$Mu),
2268 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
2269 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
2270 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
2271 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
2272 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
2273 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
2274 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2293 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst),
2294 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2298 def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>;
2299 def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>;
2300 def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>;
2301 def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>;
2302 def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>;
2336 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
2422 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2514 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
2648 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
2679 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
2683 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
2723 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
2742 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
2745 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
2750 def M2_mpyui : MInst<(outs IntRegs:$dst),
2751 (ins IntRegs:$src1, IntRegs:$src2),
2761 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
2763 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2770 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
2791 : MInst < (outs IntRegs:$dst),
2792 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
2814 [(set (i32 IntRegs:$dst),
2815 (add (mul IntRegs:$src2, u32ImmPred:$src3),
2816 IntRegs:$src1))]>, ImmRegRel;
2819 [(set (i32 IntRegs:$dst),
2820 (add (mul IntRegs:$src2, IntRegs:$src3),
2821 IntRegs:$src1))]>, ImmRegRel;
2827 [(set (i32 IntRegs:$dst),
2828 (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3),
2829 (i32 IntRegs:$src1)))]>, ImmRegRel;
2832 [(set (i32 IntRegs:$dst),
2833 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)),
2834 (i32 IntRegs:$src1)))]>, ImmRegRel;
2852 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)),
2853 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>;
2856 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))),
2857 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3046 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
3109 (ins IntRegs:$Rs, IntRegs:$Rt),
3137 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
3210 def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
3211 (i64 (anyext (i32 IntRegs:$src2))))),
3212 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
3214 def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
3215 (i64 (sext (i32 IntRegs:$src2))))),
3216 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
3226 (mul (i64 (sext (i32 IntRegs:$src2))),
3227 (i64 (sext (i32 IntRegs:$src3)))))),
3228 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3231 (mul (i64 (sext (i32 IntRegs:$src2))),
3232 (i64 (sext (i32 IntRegs:$src3)))))),
3233 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3236 (mul (i64 (anyext (i32 IntRegs:$src2))),
3237 (i64 (anyext (i32 IntRegs:$src3)))))),
3238 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3241 (mul (i64 (zext (i32 IntRegs:$src2))),
3242 (i64 (zext (i32 IntRegs:$src3)))))),
3243 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3246 (mul (i64 (anyext (i32 IntRegs:$src2))),
3247 (i64 (anyext (i32 IntRegs:$src3)))))),
3248 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3251 (mul (i64 (zext (i32 IntRegs:$src2))),
3252 (i64 (zext (i32 IntRegs:$src3)))))),
3253 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
3291 : STInst <(outs IntRegs:$_dst_),
3292 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
3326 : STInst <(outs IntRegs:$_dst_),
3327 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
3380 defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
3383 defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
3386 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3392 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3410 : STInst <(outs IntRegs:$_dst_),
3411 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
3429 def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
3430 def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
3431 def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
3434 def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
3440 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
3474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
3531 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
3534 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
3537 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
3544 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
3564 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3565 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
3567 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3568 (MI IntRegs:$Rs, 0, Value:$Rt)>;
3583 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
3584 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>;
3587 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)),
3588 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>;
3649 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
3672 : STInst <(outs IntRegs:$_dst_),
3673 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
3698 def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
3700 def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
3702 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
3704 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
3712 : NVInst < (outs IntRegs:$_dst_),
3713 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
3751 : STInstPI<(outs IntRegs:$_dst_),
3752 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4),
3756 def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>;
3757 def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3758 def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>;
3759 def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>;
3768 : STInst <(outs IntRegs:$_dst_),
3769 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
3789 def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
3790 def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
3791 def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
3793 def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
3802 : NVInst <(outs IntRegs:$_dst_),
3803 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3835 <(outs IntRegs:$_dst_),
3836 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
3858 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
3861 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
3864 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
3868 def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
3877 : NVInst <(outs IntRegs:$_dst_),
3878 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
3914 : STInstPI<(outs IntRegs:$_dst_),
3915 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3),
3919 def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>;
3920 def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3921 def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>;
3922 def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>;
3952 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
3956 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
3960 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
4029 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4030 (i32 (sub 0, (i32 IntRegs:$src))),
4031 (i32 IntRegs:$src))),
4032 (A2_abs IntRegs:$src)>;
4035 def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)),
4036 (i32 IntRegs:$src)),
4037 (sra (i32 IntRegs:$src), (i32 31)))),
4038 (A2_abs IntRegs:$src)>;
4064 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
4068 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
4073 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
4078 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
4100 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
4105 def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
4111 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
4178 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
4182 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
4205 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4221 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
4241 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4242 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4243 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4244 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4245 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4246 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4247 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
4248 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4249 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4250 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4251 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
4252 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
4258 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4275 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4293 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4294 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4295 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
4296 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
4297 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
4298 (S2_tstbit_i IntRegs:$Rs, 0)>;
4305 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
4322 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
4342 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
4343 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
4344 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
4345 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
4349 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
4350 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
4367 def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))),
4369 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))),
4371 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))),
4372 (zextloadi8 (i32 IntRegs:$b))),
4373 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
4385 def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
4399 def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
4418 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
4419 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
4420 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
4421 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
4469 def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
4470 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
4472 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
4473 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
4532 def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$fi, s32Imm:$Off), "">;
4561 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
4633 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4660 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
4703 def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
4705 def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
4706 def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
4725 def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
4727 def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
4728 def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
4732 def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
4753 : ALU32_ri<(outs IntRegs:$dst),
4776 def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4781 def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
4787 def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4793 def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4799 def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4805 def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
4813 def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
4815 [(set (i32 IntRegs:$dst),
4819 def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
4821 [(set (i32 IntRegs:$dst),
4825 def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
4827 [(set (i32 IntRegs:$dst), imm:$global) ]>;
4834 def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
4836 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
4900 def: Pat<(HexagonTCRet (i32 IntRegs:$dst)),
4901 (TCRETURNr IntRegs:$dst)>;
4904 def: Pat<(and (i32 IntRegs:$src1), 65535),
4905 (A2_zxth IntRegs:$src1)>;
4908 def: Pat<(and (i32 IntRegs:$src1), 255),
4909 (A2_zxtb IntRegs:$src1)>;
4924 (i32 IntRegs:$src3)),
4925 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
4929 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4930 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
4950 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
4952 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
4955 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
4957 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
4966 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
4967 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
4995 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
4996 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
4999 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5000 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
5010 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
5011 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
5024 def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
5025 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
5029 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
5030 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
5041 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5042 (C2_not (C2_cmpgti IntRegs:$src1,
5046 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
5047 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
5050 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5051 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
5054 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5055 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
5124 def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
5126 [(set (i32 IntRegs:$dst),
5127 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
5130 def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
5131 (i32 IntRegs:$src1)>;
5155 : SInst_acc<(outs IntRegs:$Rx),
5156 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5158 [(set (i32 IntRegs:$Rx),
5159 (OpNode2 (i32 IntRegs:$src1),
5160 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5185 : SInst_acc<(outs IntRegs:$Rx),
5186 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
5188 [(set (i32 IntRegs:$Rx),
5189 (OpNode2 (i32 IntRegs:$src1),
5190 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))],
5243 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
5247 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))],
5400 (ins RC:$src1, IntRegs:$src2),
5409 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
5419 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0,
5420 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
5421 (i32 IntRegs:$src2)))]>;
5425 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5431 (i32 IntRegs:$src2)))]>;
5464 : SInst < (outs IntRegs:$Rd),
5465 (ins DoubleRegs:$Rss, IntRegs:$Rt),
5529 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5567 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
5568 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
5618 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
5676 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
5711 def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
5712 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
5720 : SInst <(outs IntRegs:$Rx),
5721 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
5751 : SInst <(outs IntRegs:$Rx),
5752 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),