1//==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Hexagon instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14include "HexagonInstrFormats.td" 15include "HexagonOperands.td" 16 17// Pattern fragment that combines the value type and the register class 18// into a single parameter. 19// The pat frags in the definitions below need to have a named register, 20// otherwise i32 will be assumed regardless of the register class. The 21// name of the register does not matter. 22def I1 : PatLeaf<(i1 PredRegs:$R)>; 23def I32 : PatLeaf<(i32 IntRegs:$R)>; 24def I64 : PatLeaf<(i64 DoubleRegs:$R)>; 25def F32 : PatLeaf<(f32 IntRegs:$R)>; 26def F64 : PatLeaf<(f64 DoubleRegs:$R)>; 27 28// Pattern fragments to extract the low and high subregisters from a 29// 64-bit value. 30def LoReg: OutPatFrag<(ops node:$Rs), 31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>; 32def HiReg: OutPatFrag<(ops node:$Rs), 33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>; 34 35// SDNode for converting immediate C to C-1. 36def DEC_CONST_SIGNED : SDNodeXForm<imm, [{ 37 // Return the byte immediate const-1 as an SDNode. 38 int32_t imm = N->getSExtValue(); 39 return XformSToSM1Imm(imm); 40}]>; 41 42// SDNode for converting immediate C to C-2. 43def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{ 44 // Return the byte immediate const-2 as an SDNode. 45 int32_t imm = N->getSExtValue(); 46 return XformSToSM2Imm(imm); 47}]>; 48 49// SDNode for converting immediate C to C-3. 50def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{ 51 // Return the byte immediate const-3 as an SDNode. 52 int32_t imm = N->getSExtValue(); 53 return XformSToSM3Imm(imm); 54}]>; 55 56// SDNode for converting immediate C to C-1. 57def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{ 58 // Return the byte immediate const-1 as an SDNode. 59 uint32_t imm = N->getZExtValue(); 60 return XformUToUM1Imm(imm); 61}]>; 62 63//===----------------------------------------------------------------------===// 64// Compare 65//===----------------------------------------------------------------------===// 66let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1, 67 opExtendable = 2 in 68class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp> 69 : ALU32Inst <(outs PredRegs:$dst), 70 (ins IntRegs:$src1, ImmOp:$src2), 71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)", 72 [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel { 73 bits<2> dst; 74 bits<5> src1; 75 bits<10> src2; 76 let CextOpcode = mnemonic; 77 let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10); 78 let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1); 79 80 let IClass = 0b0111; 81 82 let Inst{27-24} = 0b0101; 83 let Inst{23-22} = MajOp; 84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9}); 85 let Inst{20-16} = src1; 86 let Inst{13-5} = src2{8-0}; 87 let Inst{4} = isNot; 88 let Inst{3-2} = 0b00; 89 let Inst{1-0} = dst; 90 } 91 92def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>; 93def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>; 94def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>; 95 96class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred> 97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)), 98 (MI IntRegs:$src1, ImmPred:$src2)>; 99 100def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>; 101def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>; 102def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>; 103 104//===----------------------------------------------------------------------===// 105// ALU32/ALU + 106//===----------------------------------------------------------------------===// 107// Add. 108 109def SDT_Int32Leaf : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 110def SDT_Int32Unary : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 111 112def SDTHexagonI64I32I32 : SDTypeProfile<1, 2, 113 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 114 115def HexagonCOMBINE : SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>; 116def HexagonPACKHL : SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>; 117 118let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in 119class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev, 120 bit IsComm> 121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 122 "$Rd = "#mnemonic#"($Rs, $Rt)", 123 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel { 124 let isCommutable = IsComm; 125 let BaseOpcode = mnemonic#_rr; 126 let CextOpcode = mnemonic; 127 128 bits<5> Rs; 129 bits<5> Rt; 130 bits<5> Rd; 131 132 let IClass = 0b1111; 133 let Inst{27} = 0b0; 134 let Inst{26-24} = MajOp; 135 let Inst{23-21} = MinOp; 136 let Inst{20-16} = !if(OpsRev,Rt,Rs); 137 let Inst{12-8} = !if(OpsRev,Rs,Rt); 138 let Inst{4-0} = Rd; 139} 140 141let hasSideEffects = 0, hasNewValue = 1 in 142class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp, 143 bit OpsRev, bit PredNot, bit PredNew> 144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), 145 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "# 146 "$Rd = "#mnemonic#"($Rs, $Rt)", 147 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { 148 let isPredicated = 1; 149 let isPredicatedFalse = PredNot; 150 let isPredicatedNew = PredNew; 151 let BaseOpcode = mnemonic#_rr; 152 let CextOpcode = mnemonic; 153 154 bits<2> Pu; 155 bits<5> Rs; 156 bits<5> Rt; 157 bits<5> Rd; 158 159 let IClass = 0b1111; 160 let Inst{27} = 0b1; 161 let Inst{26-24} = MajOp; 162 let Inst{23-21} = MinOp; 163 let Inst{20-16} = !if(OpsRev,Rt,Rs); 164 let Inst{13} = PredNew; 165 let Inst{12-8} = !if(OpsRev,Rs,Rt); 166 let Inst{7} = PredNot; 167 let Inst{6-5} = Pu; 168 let Inst{4-0} = Rd; 169} 170 171class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp, 172 bit OpsRev> 173 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> { 174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")"; 175} 176 177def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>; 178def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>; 179def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>; 180def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>; 181 182class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp, 183 bits<3> MinOp, bit OpsRev, bit IsComm> 184 : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> { 185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix; 186} 187 188def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>; 189def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>; 190 191let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in { 192 def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>; 193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; 194 def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>; 195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>; 196 def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>; 197 def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>; 198} 199 200let Itinerary = ALU32_3op_tc_2_SLOT0123 in 201def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>; 202 203def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>; 204def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>; 205 206multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp, 207 bit OpsRev> { 208 def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>; 209 def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>; 210 def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>; 211 def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>; 212} 213 214multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp, 215 bit OpsRev, bit IsComm> { 216 let isPredicable = 1 in 217 def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>; 218 defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>; 219} 220 221defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; 222defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; 223defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; 224defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; 225defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; 226 227// Pats for instruction selection. 228class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT> 229 : Pat<(ResT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 230 (ResT (MI IntRegs:$Rs, IntRegs:$Rt))>; 231 232def: BinOp32_pat<add, A2_add, i32>; 233def: BinOp32_pat<and, A2_and, i32>; 234def: BinOp32_pat<or, A2_or, i32>; 235def: BinOp32_pat<sub, A2_sub, i32>; 236def: BinOp32_pat<xor, A2_xor, i32>; 237 238// A few special cases producing register pairs: 239let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in { 240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>; 241 242 let isPredicable = 1 in 243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>; 244 245 // Conditional combinew uses "newt/f" instead of "t/fnew". 246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>; 247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>; 248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>; 249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>; 250} 251 252def: BinOp32_pat<HexagonCOMBINE, A2_combinew, i64>; 253def: BinOp32_pat<HexagonPACKHL, S2_packhl, i64>; 254 255let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in 256class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm> 257 : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 258 "$Pd = "#mnemonic#"($Rs, $Rt)", 259 [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { 260 let CextOpcode = mnemonic; 261 let isCommutable = IsComm; 262 bits<5> Rs; 263 bits<5> Rt; 264 bits<2> Pd; 265 266 let IClass = 0b1111; 267 let Inst{27-24} = 0b0010; 268 let Inst{22-21} = MinOp; 269 let Inst{20-16} = Rs; 270 let Inst{12-8} = Rt; 271 let Inst{4} = IsNeg; 272 let Inst{3-2} = 0b00; 273 let Inst{1-0} = Pd; 274} 275 276let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { 277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; 278 def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; 279 def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; 280} 281 282// Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 283// that reverse the order of the operands. 284class RevCmp<PatFrag F> : PatFrag<(ops node:$rhs, node:$lhs), F.Fragment>; 285 286// Pats for compares. They use PatFrags as operands, not SDNodes, 287// since seteq/setgt/etc. are defined as ParFrags. 288class T_cmp32_rr_pat<InstHexagon MI, PatFrag Op, ValueType VT> 289 : Pat<(VT (Op (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 290 (VT (MI IntRegs:$Rs, IntRegs:$Rt))>; 291 292def: T_cmp32_rr_pat<C2_cmpeq, seteq, i1>; 293def: T_cmp32_rr_pat<C2_cmpgt, setgt, i1>; 294def: T_cmp32_rr_pat<C2_cmpgtu, setugt, i1>; 295 296def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>; 297def: T_cmp32_rr_pat<C2_cmpgtu, RevCmp<setult>, i1>; 298 299let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in 300def C2_mux: ALU32_rr<(outs IntRegs:$Rd), 301 (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), 302 "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { 303 bits<5> Rd; 304 bits<2> Pu; 305 bits<5> Rs; 306 bits<5> Rt; 307 308 let CextOpcode = "mux"; 309 let InputType = "reg"; 310 let hasSideEffects = 0; 311 let IClass = 0b1111; 312 313 let Inst{27-24} = 0b0100; 314 let Inst{20-16} = Rs; 315 let Inst{12-8} = Rt; 316 let Inst{6-5} = Pu; 317 let Inst{4-0} = Rd; 318} 319 320def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))), 321 (C2_mux PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt)>; 322 323// Combines the two immediates into a double register. 324// Increase complexity to make it greater than any complexity of a combine 325// that involves a register. 326 327let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 328 isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1, 329 AddedComplexity = 75 in 330def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8), 331 "$Rdd = combine(#$s8, #$S8)", 332 [(set (i64 DoubleRegs:$Rdd), 333 (i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> { 334 bits<5> Rdd; 335 bits<8> s8; 336 bits<8> S8; 337 338 let IClass = 0b0111; 339 let Inst{27-23} = 0b11000; 340 let Inst{22-16} = S8{7-1}; 341 let Inst{13} = S8{0}; 342 let Inst{12-5} = s8; 343 let Inst{4-0} = Rdd; 344 } 345 346//===----------------------------------------------------------------------===// 347// Template class for predicated ADD of a reg and an Immediate value. 348//===----------------------------------------------------------------------===// 349let hasNewValue = 1, hasSideEffects = 0 in 350class T_Addri_Pred <bit PredNot, bit PredNew> 351 : ALU32_ri <(outs IntRegs:$Rd), 352 (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), 353 !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ", 354 ") $Rd = ")#"add($Rs, #$s8)"> { 355 bits<5> Rd; 356 bits<2> Pu; 357 bits<5> Rs; 358 bits<8> s8; 359 360 let isPredicatedNew = PredNew; 361 let IClass = 0b0111; 362 363 let Inst{27-24} = 0b0100; 364 let Inst{23} = PredNot; 365 let Inst{22-21} = Pu; 366 let Inst{20-16} = Rs; 367 let Inst{13} = PredNew; 368 let Inst{12-5} = s8; 369 let Inst{4-0} = Rd; 370 } 371 372//===----------------------------------------------------------------------===// 373// A2_addi: Add a signed immediate to a register. 374//===----------------------------------------------------------------------===// 375let hasNewValue = 1, hasSideEffects = 0 in 376class T_Addri <Operand immOp> 377 : ALU32_ri <(outs IntRegs:$Rd), 378 (ins IntRegs:$Rs, immOp:$s16), 379 "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> { 380 bits<5> Rd; 381 bits<5> Rs; 382 bits<16> s16; 383 384 let IClass = 0b1011; 385 386 let Inst{27-21} = s16{15-9}; 387 let Inst{20-16} = Rs; 388 let Inst{13-5} = s16{8-0}; 389 let Inst{4-0} = Rd; 390 } 391 392//===----------------------------------------------------------------------===// 393// Multiclass for ADD of a register and an immediate value. 394//===----------------------------------------------------------------------===// 395multiclass Addri_Pred<string mnemonic, bit PredNot> { 396 let isPredicatedFalse = PredNot in { 397 def NAME : T_Addri_Pred<PredNot, 0>; 398 // Predicate new 399 def NAME#new : T_Addri_Pred<PredNot, 1>; 400 } 401} 402 403let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in 404multiclass Addri_base<string mnemonic, SDNode OpNode> { 405 let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in { 406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in 407 def A2_#NAME : T_Addri<s16Ext>; 408 409 let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in { 410 defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>; 411 defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>; 412 } 413 } 414} 415 416defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel; 417 418def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)), 419 (i32 (A2_addi I32:$Rs, imm:$s16))>; 420 421//===----------------------------------------------------------------------===// 422// Template class used for the following ALU32 instructions. 423// Rd=and(Rs,#s10) 424// Rd=or(Rs,#s10) 425//===----------------------------------------------------------------------===// 426let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10, 427InputType = "imm", hasNewValue = 1 in 428class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp> 429 : ALU32_ri <(outs IntRegs:$Rd), 430 (ins IntRegs:$Rs, s10Ext:$s10), 431 "$Rd = "#mnemonic#"($Rs, #$s10)" , 432 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> { 433 bits<5> Rd; 434 bits<5> Rs; 435 bits<10> s10; 436 let CextOpcode = mnemonic; 437 438 let IClass = 0b0111; 439 440 let Inst{27-24} = 0b0110; 441 let Inst{23-22} = MinOp; 442 let Inst{21} = s10{9}; 443 let Inst{20-16} = Rs; 444 let Inst{13-5} = s10{8-0}; 445 let Inst{4-0} = Rd; 446 } 447 448def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel; 449def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel; 450 451// Subtract register from immediate 452// Rd32=sub(#s10,Rs32) 453let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1, 454 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in 455def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs), 456 "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel { 457 bits<5> Rd; 458 bits<10> s10; 459 bits<5> Rs; 460 461 let IClass = 0b0111; 462 463 let Inst{27-22} = 0b011001; 464 let Inst{21} = s10{9}; 465 let Inst{20-16} = Rs; 466 let Inst{13-5} = s10{8-0}; 467 let Inst{4-0} = Rd; 468 } 469 470// Nop. 471let hasSideEffects = 0 in 472def A2_nop: ALU32Inst <(outs), (ins), "nop" > { 473 let IClass = 0b0111; 474 let Inst{27-24} = 0b1111; 475} 476 477def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs), 478 (A2_subri imm:$s10, IntRegs:$Rs)>; 479 480// Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs). 481def: Pat<(not (i32 IntRegs:$src1)), 482 (A2_subri -1, IntRegs:$src1)>; 483 484let hasSideEffects = 0, hasNewValue = 1 in 485class T_tfr16<bit isHi> 486 : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16), 487 "$Rx"#!if(isHi, ".h", ".l")#" = #$u16", 488 [], "$src1 = $Rx" > { 489 bits<5> Rx; 490 bits<16> u16; 491 492 let IClass = 0b0111; 493 let Inst{27-26} = 0b00; 494 let Inst{25-24} = !if(isHi, 0b10, 0b01); 495 let Inst{23-22} = u16{15-14}; 496 let Inst{21} = 0b1; 497 let Inst{20-16} = Rx; 498 let Inst{13-0} = u16{13-0}; 499 } 500 501def A2_tfril: T_tfr16<0>; 502def A2_tfrih: T_tfr16<1>; 503 504// Conditional transfer is an alias to conditional "Rd = add(Rs, #0)". 505let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in 506class T_tfr_pred<bit isPredNot, bit isPredNew> 507 : ALU32Inst<(outs IntRegs:$dst), 508 (ins PredRegs:$src1, IntRegs:$src2), 509 "if ("#!if(isPredNot, "!", "")# 510 "$src1"#!if(isPredNew, ".new", "")# 511 ") $dst = $src2"> { 512 bits<5> dst; 513 bits<2> src1; 514 bits<5> src2; 515 516 let isPredicatedFalse = isPredNot; 517 let isPredicatedNew = isPredNew; 518 let IClass = 0b0111; 519 520 let Inst{27-24} = 0b0100; 521 let Inst{23} = isPredNot; 522 let Inst{13} = isPredNew; 523 let Inst{12-5} = 0; 524 let Inst{4-0} = dst; 525 let Inst{22-21} = src1; 526 let Inst{20-16} = src2; 527 } 528 529let isPredicable = 1 in 530class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src), 531 "$dst = $src"> { 532 bits<5> dst; 533 bits<5> src; 534 535 let IClass = 0b0111; 536 537 let Inst{27-21} = 0b0000011; 538 let Inst{20-16} = src; 539 let Inst{13} = 0b0; 540 let Inst{4-0} = dst; 541 } 542 543let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in 544multiclass tfr_base<string CextOp> { 545 let CextOpcode = CextOp, BaseOpcode = CextOp in { 546 def NAME : T_tfr; 547 548 // Predicate 549 def t : T_tfr_pred<0, 0>; 550 def f : T_tfr_pred<1, 0>; 551 // Predicate new 552 def tnew : T_tfr_pred<0, 1>; 553 def fnew : T_tfr_pred<1, 1>; 554 } 555} 556 557// Assembler mapped to C2_ccombinew[t|f|newt|newf]. 558// Please don't add bits to this instruction as it'll be converted into 559// 'combine' before object code emission. 560let isPredicated = 1 in 561class T_tfrp_pred<bit PredNot, bit PredNew> 562 : ALU32_rr <(outs DoubleRegs:$dst), 563 (ins PredRegs:$src1, DoubleRegs:$src2), 564 "if ("#!if(PredNot, "!", "")#"$src1" 565 #!if(PredNew, ".new", "")#") $dst = $src2" > { 566 let isPredicatedFalse = PredNot; 567 let isPredicatedNew = PredNew; 568 } 569 570// Assembler mapped to A2_combinew. 571// Please don't add bits to this instruction as it'll be converted into 572// 'combine' before object code emission. 573class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst), 574 (ins DoubleRegs:$src), 575 "$dst = $src">; 576 577let hasSideEffects = 0 in 578multiclass TFR64_base<string BaseName> { 579 let BaseOpcode = BaseName in { 580 let isPredicable = 1 in 581 def NAME : T_tfrp; 582 // Predicate 583 def t : T_tfrp_pred <0, 0>; 584 def f : T_tfrp_pred <1, 0>; 585 // Predicate new 586 def tnew : T_tfrp_pred <0, 1>; 587 def fnew : T_tfrp_pred <1, 1>; 588 } 589} 590 591let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12, 592 isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR", 593 hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in 594class T_TFRI_Pred<bit PredNot, bit PredNew> 595 : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12), 596 "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12", 597 [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { 598 let isPredicatedFalse = PredNot; 599 let isPredicatedNew = PredNew; 600 601 bits<5> Rd; 602 bits<2> Pu; 603 bits<12> s12; 604 605 let IClass = 0b0111; 606 let Inst{27-24} = 0b1110; 607 let Inst{23} = PredNot; 608 let Inst{22-21} = Pu; 609 let Inst{20} = 0b0; 610 let Inst{19-16,12-5} = s12; 611 let Inst{13} = PredNew; 612 let Inst{4-0} = Rd; 613} 614 615def C2_cmoveit : T_TFRI_Pred<0, 0>; 616def C2_cmoveif : T_TFRI_Pred<1, 0>; 617def C2_cmovenewit : T_TFRI_Pred<0, 1>; 618def C2_cmovenewif : T_TFRI_Pred<1, 1>; 619 620let InputType = "imm", isExtendable = 1, isExtentSigned = 1, 621 CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0, 622 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1, 623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in 624def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16", 625 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>, 626 ImmRegRel, PredRel { 627 bits<5> Rd; 628 bits<16> s16; 629 630 let IClass = 0b0111; 631 let Inst{27-24} = 0b1000; 632 let Inst{23-22,20-16,13-5} = s16; 633 let Inst{4-0} = Rd; 634} 635 636defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel; 637let isAsmParserOnly = 1 in 638defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel; 639 640// Assembler mapped 641let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 642 isAsmParserOnly = 1 in 643def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1), 644 "$dst = #$src1", 645 [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>; 646 647// TODO: see if this instruction can be deleted.. 648let isExtendable = 1, opExtendable = 1, opExtentBits = 6, 649 isAsmParserOnly = 1 in { 650def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1), 651 "$dst = #$src1">; 652def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), 653 (ins s8Ext:$src1, s8Imm:$src2), 654 "$dst = combine(##$src1, #$src2)">; 655} 656 657//===----------------------------------------------------------------------===// 658// ALU32/ALU - 659//===----------------------------------------------------------------------===// 660 661 662//===----------------------------------------------------------------------===// 663// ALU32/PERM + 664//===----------------------------------------------------------------------===// 665// Scalar mux register immediate. 666let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX", 667 InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in 668class T_MUX1 <bit MajOp, dag ins, string AsmStr> 669 : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel { 670 bits<5> Rd; 671 bits<2> Pu; 672 bits<8> s8; 673 bits<5> Rs; 674 675 let IClass = 0b0111; 676 let Inst{27-24} = 0b0011; 677 let Inst{23} = MajOp; 678 let Inst{22-21} = Pu; 679 let Inst{20-16} = Rs; 680 let Inst{13} = 0b0; 681 let Inst{12-5} = s8; 682 let Inst{4-0} = Rd; 683} 684 685let opExtendable = 2 in 686def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs), 687 "$Rd = mux($Pu, #$s8, $Rs)">; 688 689let opExtendable = 3 in 690def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), 691 "$Rd = mux($Pu, $Rs, #$s8)">; 692 693def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)), 694 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>; 695 696def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)), 697 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>; 698 699// C2_muxii: Scalar mux immediates. 700let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, 701 opExtentBits = 8, opExtendable = 2 in 702def C2_muxii: ALU32Inst <(outs IntRegs:$Rd), 703 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8), 704 "$Rd = mux($Pu, #$s8, #$S8)" , 705 [(set (i32 IntRegs:$Rd), 706 (i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > { 707 bits<5> Rd; 708 bits<2> Pu; 709 bits<8> s8; 710 bits<8> S8; 711 712 let IClass = 0b0111; 713 714 let Inst{27-25} = 0b101; 715 let Inst{24-23} = Pu; 716 let Inst{22-16} = S8{7-1}; 717 let Inst{13} = S8{0}; 718 let Inst{12-5} = s8; 719 let Inst{4-0} = Rd; 720 } 721 722let isCodeGenOnly = 1, isPseudo = 1 in 723def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd), 724 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), 725 ".error \"should not emit\" ", []>; 726 727 728//===----------------------------------------------------------------------===// 729// template class for non-predicated alu32_2op instructions 730// - aslh, asrh, sxtb, sxth, zxth 731//===----------------------------------------------------------------------===// 732let hasNewValue = 1, opNewValue = 0 in 733class T_ALU32_2op <string mnemonic, bits<3> minOp> : 734 ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), 735 "$Rd = "#mnemonic#"($Rs)", [] > { 736 bits<5> Rd; 737 bits<5> Rs; 738 739 let IClass = 0b0111; 740 741 let Inst{27-24} = 0b0000; 742 let Inst{23-21} = minOp; 743 let Inst{13} = 0b0; 744 let Inst{4-0} = Rd; 745 let Inst{20-16} = Rs; 746} 747 748//===----------------------------------------------------------------------===// 749// template class for predicated alu32_2op instructions 750// - aslh, asrh, sxtb, sxth, zxtb, zxth 751//===----------------------------------------------------------------------===// 752let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 753class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot, 754 bit isPredNew > : 755 ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs), 756 !if(isPredNot, "if (!$Pu", "if ($Pu") 757 #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> { 758 bits<5> Rd; 759 bits<2> Pu; 760 bits<5> Rs; 761 762 let IClass = 0b0111; 763 764 let Inst{27-24} = 0b0000; 765 let Inst{23-21} = minOp; 766 let Inst{13} = 0b1; 767 let Inst{11} = isPredNot; 768 let Inst{10} = isPredNew; 769 let Inst{4-0} = Rd; 770 let Inst{9-8} = Pu; 771 let Inst{20-16} = Rs; 772} 773 774multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> { 775 let isPredicatedFalse = PredNot in { 776 def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>; 777 778 // Predicate new 779 let isPredicatedNew = 1 in 780 def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>; 781 } 782} 783 784multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { 785 let BaseOpcode = mnemonic in { 786 let isPredicable = 1, hasSideEffects = 0 in 787 def A2_#NAME : T_ALU32_2op<mnemonic, minOp>; 788 789 let isPredicated = 1, hasSideEffects = 0 in { 790 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; 791 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; 792 } 793 } 794} 795 796defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; 797defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel; 798defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; 799defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; 800defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; 801 802// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). 803// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has 804// predicated forms while 'and' doesn't. Since integrated assembler can't 805// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where 806// immediate operand is set to '255'. 807 808let hasNewValue = 1, opNewValue = 0 in 809class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs), 810 "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255) 811 bits<5> Rd; 812 bits<5> Rs; 813 bits<10> s10 = 255; 814 815 let IClass = 0b0111; 816 817 let Inst{27-22} = 0b011000; 818 let Inst{4-0} = Rd; 819 let Inst{20-16} = Rs; 820 let Inst{21} = s10{9}; 821 let Inst{13-5} = s10{8-0}; 822} 823 824//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255) 825multiclass ZXTB_base <string mnemonic, bits<3> minOp> { 826 let BaseOpcode = mnemonic in { 827 let isPredicable = 1, hasSideEffects = 0 in 828 def A2_#NAME : T_ZXTB; 829 830 let isPredicated = 1, hasSideEffects = 0 in { 831 defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; 832 defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; 833 } 834 } 835} 836 837defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel; 838 839def: Pat<(shl I32:$src1, (i32 16)), (A2_aslh I32:$src1)>; 840def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>; 841def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>; 842def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>; 843 844//===----------------------------------------------------------------------===// 845// Template class for vector add and avg 846//===----------------------------------------------------------------------===// 847 848class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp, 849 bit isSat, bit isRnd, bit isCrnd, bit SwapOps > 850 : ALU64_rr < (outs DoubleRegs:$Rdd), 851 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 852 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "") 853 #!if(isCrnd,":crnd","") 854 #!if(isSat, ":sat", ""), 855 [], "", ALU64_tc_2_SLOT23 > { 856 bits<5> Rdd; 857 bits<5> Rss; 858 bits<5> Rtt; 859 860 let IClass = 0b1101; 861 862 let Inst{27-24} = 0b0011; 863 let Inst{23-21} = majOp; 864 let Inst{20-16} = !if (SwapOps, Rtt, Rss); 865 let Inst{12-8} = !if (SwapOps, Rss, Rtt); 866 let Inst{7-5} = minOp; 867 let Inst{4-0} = Rdd; 868 } 869 870// ALU64 - Vector add 871// Rdd=vadd[u][bhw](Rss,Rtt) 872let Itinerary = ALU64_tc_1_SLOT23 in { 873 def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>; 874 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; 875 def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>; 876} 877 878// Rdd=vadd[u][bhw](Rss,Rtt):sat 879let Defs = [USR_OVF] in { 880 def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>; 881 def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>; 882 def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>; 883 def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>; 884} 885 886// ALU64 - Vector average 887// Rdd=vavg[u][bhw](Rss,Rtt) 888let Itinerary = ALU64_tc_1_SLOT23 in { 889 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; 890 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; 891 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; 892 def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>; 893 def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>; 894} 895 896// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd] 897def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; 898def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; 899def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; 900def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; 901 902def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>; 903def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; 904def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>; 905 906// Rdd=vnavg[bh](Rss,Rtt) 907let Itinerary = ALU64_tc_1_SLOT23 in { 908 def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>; 909 def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>; 910} 911 912// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat 913let Defs = [USR_OVF] in { 914 def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>; 915 def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>; 916 def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>; 917 def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>; 918} 919 920// Rdd=vsub[u][bh](Rss,Rtt) 921let Itinerary = ALU64_tc_1_SLOT23 in { 922 def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>; 923 def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>; 924 def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>; 925} 926 927// Rdd=vsub[u][bh](Rss,Rtt):sat 928let Defs = [USR_OVF] in { 929 def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>; 930 def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>; 931 def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>; 932 def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>; 933} 934 935// Rdd=vmax[u][bhw](Rss,Rtt) 936def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>; 937def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>; 938def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>; 939def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>; 940def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>; 941def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>; 942 943// Rdd=vmin[u][bhw](Rss,Rtt) 944def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>; 945def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>; 946def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>; 947def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>; 948def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>; 949def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>; 950 951//===----------------------------------------------------------------------===// 952// Template class for vector compare 953//===----------------------------------------------------------------------===// 954let hasSideEffects = 0 in 955class T_vcmp <string Str, bits<4> minOp> 956 : ALU64_rr <(outs PredRegs:$Pd), 957 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 958 "$Pd = "#Str#"($Rss, $Rtt)", [], 959 "", ALU64_tc_2early_SLOT23> { 960 bits<2> Pd; 961 bits<5> Rss; 962 bits<5> Rtt; 963 964 let IClass = 0b1101; 965 966 let Inst{27-23} = 0b00100; 967 let Inst{13} = minOp{3}; 968 let Inst{7-5} = minOp{2-0}; 969 let Inst{1-0} = Pd; 970 let Inst{20-16} = Rss; 971 let Inst{12-8} = Rtt; 972 } 973 974class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T> 975 : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))), 976 (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>; 977 978// Vector compare bytes 979def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>; 980def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>; 981 982// Vector compare halfwords 983def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>; 984def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>; 985def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>; 986 987// Vector compare words 988def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>; 989def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>; 990def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>; 991 992def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>; 993def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>; 994def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>; 995def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>; 996def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>; 997def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>; 998def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>; 999def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>; 1000 1001//===----------------------------------------------------------------------===// 1002// ALU32/PERM - 1003//===----------------------------------------------------------------------===// 1004 1005 1006//===----------------------------------------------------------------------===// 1007// ALU32/PRED + 1008//===----------------------------------------------------------------------===// 1009// No bits needed. If cmp.ge is found the assembler parser will 1010// transform it to cmp.gt subtracting 1 from the immediate. 1011let isPseudo = 1 in { 1012def C2_cmpgei: ALU32Inst < 1013 (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8), 1014 "$Pd = cmp.ge($Rs, #$s8)">; 1015def C2_cmpgeui: ALU32Inst < 1016 (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8), 1017 "$Pd = cmp.geu($Rs, #$s8)">; 1018} 1019 1020 1021//===----------------------------------------------------------------------===// 1022// ALU32/PRED - 1023//===----------------------------------------------------------------------===// 1024 1025 1026//===----------------------------------------------------------------------===// 1027// ALU64/ALU + 1028//===----------------------------------------------------------------------===// 1029// Add. 1030//===----------------------------------------------------------------------===// 1031// Template Class 1032// Add/Subtract halfword 1033// Rd=add(Rt.L,Rs.[HL])[:sat] 1034// Rd=sub(Rt.L,Rs.[HL])[:sat] 1035// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] 1036// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] 1037//===----------------------------------------------------------------------===// 1038 1039let hasNewValue = 1, opNewValue = 0 in 1040class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub> 1041 : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), 1042 "$Rd = "#!if(isSub,"sub","add")#"($Rt." 1043 #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs." 1044 #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)")) 1045 #!if(isSat,":sat","") 1046 #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> { 1047 bits<5> Rd; 1048 bits<5> Rt; 1049 bits<5> Rs; 1050 let IClass = 0b1101; 1051 1052 let Inst{27-23} = 0b01010; 1053 let Inst{22} = hasShift; 1054 let Inst{21} = isSub; 1055 let Inst{7} = isSat; 1056 let Inst{6-5} = LHbits; 1057 let Inst{4-0} = Rd; 1058 let Inst{12-8} = Rt; 1059 let Inst{20-16} = Rs; 1060 } 1061 1062//Rd=sub(Rt.L,Rs.[LH]) 1063def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>; 1064def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>; 1065 1066//Rd=add(Rt.L,Rs.[LH]) 1067def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>; 1068def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>; 1069 1070let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { 1071 //Rd=sub(Rt.L,Rs.[LH]):sat 1072 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>; 1073 def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>; 1074 1075 //Rd=add(Rt.L,Rs.[LH]):sat 1076 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>; 1077 def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>; 1078} 1079 1080//Rd=sub(Rt.[LH],Rs.[LH]):<<16 1081def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>; 1082def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>; 1083def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>; 1084def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>; 1085 1086//Rd=add(Rt.[LH],Rs.[LH]):<<16 1087def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>; 1088def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>; 1089def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>; 1090def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>; 1091 1092let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { 1093 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 1094 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>; 1095 def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>; 1096 def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>; 1097 def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>; 1098 1099 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 1100 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>; 1101 def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>; 1102 def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>; 1103 def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>; 1104} 1105 1106// Add halfword. 1107def: Pat<(sext_inreg (add I32:$src1, I32:$src2), i16), 1108 (A2_addh_l16_ll I32:$src1, I32:$src2)>; 1109 1110def: Pat<(sra (add (shl I32:$src1, (i32 16)), I32:$src2), (i32 16)), 1111 (A2_addh_l16_hl I32:$src1, I32:$src2)>; 1112 1113def: Pat<(shl (add I32:$src1, I32:$src2), (i32 16)), 1114 (A2_addh_h16_ll I32:$src1, I32:$src2)>; 1115 1116// Subtract halfword. 1117def: Pat<(sext_inreg (sub I32:$src1, I32:$src2), i16), 1118 (A2_subh_l16_ll I32:$src1, I32:$src2)>; 1119 1120def: Pat<(shl (sub I32:$src1, I32:$src2), (i32 16)), 1121 (A2_subh_h16_ll I32:$src1, I32:$src2)>; 1122 1123let hasSideEffects = 0, hasNewValue = 1 in 1124def S2_parityp: ALU64Inst<(outs IntRegs:$Rd), 1125 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1126 "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { 1127 bits<5> Rd; 1128 bits<5> Rs; 1129 bits<5> Rt; 1130 1131 let IClass = 0b1101; 1132 let Inst{27-24} = 0b0000; 1133 let Inst{20-16} = Rs; 1134 let Inst{12-8} = Rt; 1135 let Inst{4-0} = Rd; 1136} 1137 1138let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in 1139class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned > 1140 : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), 1141 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") 1142 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { 1143 bits<5> Rd; 1144 bits<5> Rt; 1145 bits<5> Rs; 1146 1147 let IClass = 0b1101; 1148 1149 let Inst{27-23} = 0b01011; 1150 let Inst{22-21} = !if(isMax, 0b10, 0b01); 1151 let Inst{7} = isUnsigned; 1152 let Inst{4-0} = Rd; 1153 let Inst{12-8} = !if(isMax, Rs, Rt); 1154 let Inst{20-16} = !if(isMax, Rt, Rs); 1155 } 1156 1157def A2_min : T_XTYPE_MIN_MAX < 0, 0 >; 1158def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >; 1159def A2_max : T_XTYPE_MIN_MAX < 1, 0 >; 1160def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >; 1161 1162// Here, depending on the operand being selected, we'll either generate a 1163// min or max instruction. 1164// Ex: 1165// (a>b)?a:b --> max(a,b) => Here check performed is '>' and the value selected 1166// is the larger of two. So, the corresponding HexagonInst is passed in 'Inst'. 1167// (a>b)?b:a --> min(a,b) => Here check performed is '>' but the smaller value 1168// is selected and the corresponding HexagonInst is passed in 'SwapInst'. 1169 1170multiclass T_MinMax_pats <PatFrag Op, RegisterClass RC, ValueType VT, 1171 InstHexagon Inst, InstHexagon SwapInst> { 1172 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))), 1173 (VT RC:$src1), (VT RC:$src2)), 1174 (Inst RC:$src1, RC:$src2)>; 1175 def: Pat<(select (i1 (Op (VT RC:$src1), (VT RC:$src2))), 1176 (VT RC:$src2), (VT RC:$src1)), 1177 (SwapInst RC:$src1, RC:$src2)>; 1178} 1179 1180 1181multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> { 1182 defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>; 1183 1184 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1), 1185 (i32 PositiveHalfWord:$src2))), 1186 (i32 PositiveHalfWord:$src1), 1187 (i32 PositiveHalfWord:$src2))), i16), 1188 (Inst IntRegs:$src1, IntRegs:$src2)>; 1189 1190 def: Pat<(sext_inreg (i32 (select (i1 (Op (i32 PositiveHalfWord:$src1), 1191 (i32 PositiveHalfWord:$src2))), 1192 (i32 PositiveHalfWord:$src2), 1193 (i32 PositiveHalfWord:$src1))), i16), 1194 (SwapInst IntRegs:$src1, IntRegs:$src2)>; 1195} 1196 1197let AddedComplexity = 200 in { 1198 defm: MinMax_pats<setge, A2_max, A2_min>; 1199 defm: MinMax_pats<setgt, A2_max, A2_min>; 1200 defm: MinMax_pats<setle, A2_min, A2_max>; 1201 defm: MinMax_pats<setlt, A2_min, A2_max>; 1202 defm: MinMax_pats<setuge, A2_maxu, A2_minu>; 1203 defm: MinMax_pats<setugt, A2_maxu, A2_minu>; 1204 defm: MinMax_pats<setule, A2_minu, A2_maxu>; 1205 defm: MinMax_pats<setult, A2_minu, A2_maxu>; 1206} 1207 1208class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm> 1209 : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1210 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> { 1211 let isCompare = 1; 1212 let isCommutable = IsComm; 1213 let hasSideEffects = 0; 1214 1215 bits<2> Pd; 1216 bits<5> Rs; 1217 bits<5> Rt; 1218 1219 let IClass = 0b1101; 1220 let Inst{27-21} = 0b0010100; 1221 let Inst{20-16} = Rs; 1222 let Inst{12-8} = Rt; 1223 let Inst{7-5} = MinOp; 1224 let Inst{1-0} = Pd; 1225} 1226 1227def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>; 1228def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>; 1229def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>; 1230 1231class T_cmp64_rr_pat<InstHexagon MI, PatFrag CmpOp> 1232 : Pat<(i1 (CmpOp (i64 DoubleRegs:$Rs), (i64 DoubleRegs:$Rt))), 1233 (i1 (MI DoubleRegs:$Rs, DoubleRegs:$Rt))>; 1234 1235def: T_cmp64_rr_pat<C2_cmpeqp, seteq>; 1236def: T_cmp64_rr_pat<C2_cmpgtp, setgt>; 1237def: T_cmp64_rr_pat<C2_cmpgtup, setugt>; 1238def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>; 1239def: T_cmp64_rr_pat<C2_cmpgtup, RevCmp<setult>>; 1240 1241def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd), 1242 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), 1243 "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { 1244 let hasSideEffects = 0; 1245 1246 bits<5> Rd; 1247 bits<2> Pu; 1248 bits<5> Rs; 1249 bits<5> Rt; 1250 1251 let IClass = 0b1101; 1252 let Inst{27-24} = 0b0001; 1253 let Inst{20-16} = Rs; 1254 let Inst{12-8} = Rt; 1255 let Inst{6-5} = Pu; 1256 let Inst{4-0} = Rd; 1257} 1258 1259class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType, 1260 bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm, 1261 string Op2Pfx> 1262 : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), 1263 "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [], 1264 "", ALU64_tc_1_SLOT23> { 1265 let hasSideEffects = 0; 1266 let isCommutable = IsComm; 1267 1268 bits<5> Rs; 1269 bits<5> Rt; 1270 bits<5> Rd; 1271 1272 let IClass = 0b1101; 1273 let Inst{27-24} = RegType; 1274 let Inst{23-21} = MajOp; 1275 let Inst{20-16} = !if (OpsRev,Rt,Rs); 1276 let Inst{12-8} = !if (OpsRev,Rs,Rt); 1277 let Inst{7-5} = MinOp; 1278 let Inst{4-0} = Rd; 1279} 1280 1281class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat, 1282 bit OpsRev, bit IsComm> 1283 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev, 1284 IsComm, "">; 1285 1286def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>; 1287def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>; 1288 1289def: Pat<(i64 (add I64:$Rs, I64:$Rt)), (A2_addp I64:$Rs, I64:$Rt)>; 1290def: Pat<(i64 (sub I64:$Rs, I64:$Rt)), (A2_subp I64:$Rs, I64:$Rt)>; 1291 1292class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm, 1293 bit IsNeg> 1294 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm, 1295 !if(IsNeg,"~","")>; 1296 1297def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>; 1298def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>; 1299def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>; 1300 1301def: Pat<(i64 (and I64:$Rs, I64:$Rt)), (A2_andp I64:$Rs, I64:$Rt)>; 1302def: Pat<(i64 (or I64:$Rs, I64:$Rt)), (A2_orp I64:$Rs, I64:$Rt)>; 1303def: Pat<(i64 (xor I64:$Rs, I64:$Rt)), (A2_xorp I64:$Rs, I64:$Rt)>; 1304 1305//===----------------------------------------------------------------------===// 1306// ALU64/ALU - 1307//===----------------------------------------------------------------------===// 1308 1309//===----------------------------------------------------------------------===// 1310// ALU64/BIT + 1311//===----------------------------------------------------------------------===// 1312// 1313//===----------------------------------------------------------------------===// 1314// ALU64/BIT - 1315//===----------------------------------------------------------------------===// 1316 1317//===----------------------------------------------------------------------===// 1318// ALU64/PERM + 1319//===----------------------------------------------------------------------===// 1320// 1321//===----------------------------------------------------------------------===// 1322// ALU64/PERM - 1323//===----------------------------------------------------------------------===// 1324 1325//===----------------------------------------------------------------------===// 1326// CR + 1327//===----------------------------------------------------------------------===// 1328// Logical reductions on predicates. 1329 1330// Looping instructions. 1331 1332// Pipelined looping instructions. 1333 1334// Logical operations on predicates. 1335let hasSideEffects = 0 in 1336class T_LOGICAL_1OP<string MnOp, bits<2> OpBits> 1337 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps), 1338 "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> { 1339 bits<2> Pd; 1340 bits<2> Ps; 1341 1342 let IClass = 0b0110; 1343 let Inst{27-23} = 0b10111; 1344 let Inst{22-21} = OpBits; 1345 let Inst{20} = 0b0; 1346 let Inst{17-16} = Ps; 1347 let Inst{13} = 0b0; 1348 let Inst{1-0} = Pd; 1349} 1350 1351def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>; 1352def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>; 1353def C2_not : T_LOGICAL_1OP<"not", 0b10>; 1354 1355def: Pat<(i1 (not (i1 PredRegs:$Ps))), 1356 (C2_not PredRegs:$Ps)>; 1357 1358let hasSideEffects = 0 in 1359class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev> 1360 : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt), 1361 "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)", 1362 [], "", CR_tc_2early_SLOT23> { 1363 bits<2> Pd; 1364 bits<2> Ps; 1365 bits<2> Pt; 1366 1367 let IClass = 0b0110; 1368 let Inst{27-24} = 0b1011; 1369 let Inst{23-21} = OpBits; 1370 let Inst{20} = 0b0; 1371 let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some 1372 let Inst{13} = 0b0; // instructions. 1373 let Inst{9-8} = !if(Rev,Ps,Pt); 1374 let Inst{1-0} = Pd; 1375} 1376 1377def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>; 1378def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>; 1379def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>; 1380def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>; 1381def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>; 1382 1383def: Pat<(i1 (and I1:$Ps, I1:$Pt)), (C2_and I1:$Ps, I1:$Pt)>; 1384def: Pat<(i1 (or I1:$Ps, I1:$Pt)), (C2_or I1:$Ps, I1:$Pt)>; 1385def: Pat<(i1 (xor I1:$Ps, I1:$Pt)), (C2_xor I1:$Ps, I1:$Pt)>; 1386def: Pat<(i1 (and I1:$Ps, (not I1:$Pt))), (C2_andn I1:$Ps, I1:$Pt)>; 1387def: Pat<(i1 (or I1:$Ps, (not I1:$Pt))), (C2_orn I1:$Ps, I1:$Pt)>; 1388 1389let hasSideEffects = 0, hasNewValue = 1 in 1390def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt), 1391 "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> { 1392 bits<5> Rd; 1393 bits<2> Ps; 1394 bits<2> Pt; 1395 1396 let IClass = 0b1000; 1397 let Inst{27-24} = 0b1001; 1398 let Inst{22-21} = 0b00; 1399 let Inst{17-16} = Ps; 1400 let Inst{9-8} = Pt; 1401 let Inst{4-0} = Rd; 1402} 1403 1404let hasSideEffects = 0 in 1405def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt), 1406 "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> { 1407 bits<5> Rd; 1408 bits<2> Pt; 1409 1410 let IClass = 0b1000; 1411 let Inst{27-24} = 0b0110; 1412 let Inst{9-8} = Pt; 1413 let Inst{4-0} = Rd; 1414} 1415 1416// User control register transfer. 1417//===----------------------------------------------------------------------===// 1418// CR - 1419//===----------------------------------------------------------------------===// 1420 1421//===----------------------------------------------------------------------===// 1422// JR + 1423//===----------------------------------------------------------------------===// 1424 1425def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, 1426 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 1427def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; 1428 1429def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 1430def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>; 1431 1432class CondStr<string CReg, bit True, bit New> { 1433 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; 1434} 1435class JumpOpcStr<string Mnemonic, bit New, bit Taken> { 1436 string S = Mnemonic # !if(Taken, ":t", !if(New, ":nt", "")); 1437} 1438 1439let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, 1440 isPredicable = 1, 1441 isExtendable = 1, opExtendable = 0, isExtentSigned = 1, 1442 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in 1443class T_JMP<string ExtStr> 1444 : JInst<(outs), (ins brtarget:$dst), 1445 "jump " # ExtStr # "$dst", 1446 [], "", J_tc_2early_SLOT23> { 1447 bits<24> dst; 1448 let IClass = 0b0101; 1449 1450 let Inst{27-25} = 0b100; 1451 let Inst{24-16} = dst{23-15}; 1452 let Inst{13-1} = dst{14-2}; 1453} 1454 1455let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1, 1456 isExtendable = 1, opExtendable = 1, isExtentSigned = 1, 1457 opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in 1458class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr> 1459 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst), 1460 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # 1461 JumpOpcStr<"jump", isPredNew, isTak>.S # " " # 1462 ExtStr # "$dst", 1463 [], "", J_tc_2early_SLOT23>, ImmRegRel { 1464 let isTaken = isTak; 1465 let isPredicatedFalse = PredNot; 1466 let isPredicatedNew = isPredNew; 1467 bits<2> src; 1468 bits<17> dst; 1469 1470 let IClass = 0b0101; 1471 1472 let Inst{27-24} = 0b1100; 1473 let Inst{21} = PredNot; 1474 let Inst{12} = isTak; 1475 let Inst{11} = isPredNew; 1476 let Inst{9-8} = src; 1477 let Inst{23-22} = dst{16-15}; 1478 let Inst{20-16} = dst{14-10}; 1479 let Inst{13} = dst{9}; 1480 let Inst{7-1} = dst{8-2}; 1481 } 1482 1483multiclass JMP_Pred<bit PredNot, string ExtStr> { 1484 def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken 1485 // Predicate new 1486 def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken 1487 def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken 1488} 1489 1490multiclass JMP_base<string BaseOp, string ExtStr> { 1491 let BaseOpcode = BaseOp in { 1492 def NAME : T_JMP<ExtStr>; 1493 defm t : JMP_Pred<0, ExtStr>; 1494 defm f : JMP_Pred<1, ExtStr>; 1495 } 1496} 1497 1498// Jumps to address stored in a register, JUMPR_MISC 1499// if ([[!]P[.new]]) jumpr[:t/nt] Rs 1500let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], 1501 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in 1502class T_JMPr 1503 : JRInst<(outs), (ins IntRegs:$dst), 1504 "jumpr $dst", [], "", J_tc_2early_SLOT2> { 1505 bits<5> dst; 1506 1507 let IClass = 0b0101; 1508 let Inst{27-21} = 0b0010100; 1509 let Inst{20-16} = dst; 1510} 1511 1512let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, 1513 hasSideEffects = 0, InputType = "reg" in 1514class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> 1515 : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst), 1516 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # 1517 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [], 1518 "", J_tc_2early_SLOT2> { 1519 1520 let isTaken = isTak; 1521 let isPredicatedFalse = PredNot; 1522 let isPredicatedNew = isPredNew; 1523 bits<2> src; 1524 bits<5> dst; 1525 1526 let IClass = 0b0101; 1527 1528 let Inst{27-22} = 0b001101; 1529 let Inst{21} = PredNot; 1530 let Inst{20-16} = dst; 1531 let Inst{12} = isTak; 1532 let Inst{11} = isPredNew; 1533 let Inst{9-8} = src; 1534} 1535 1536multiclass JMPR_Pred<bit PredNot> { 1537 def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken 1538 // Predicate new 1539 def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken 1540 def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken 1541} 1542 1543multiclass JMPR_base<string BaseOp> { 1544 let BaseOpcode = BaseOp in { 1545 def NAME : T_JMPr; 1546 defm t : JMPR_Pred<0>; 1547 defm f : JMPR_Pred<1>; 1548 } 1549} 1550 1551let isCall = 1, hasSideEffects = 1 in 1552class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, 1553 dag InputDag = (ins IntRegs:$Rs)> 1554 : JRInst<(outs), InputDag, 1555 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", 1556 "if ($Pu) callr $Rs"), 1557 "callr $Rs"), 1558 [], "", J_tc_2early_SLOT2> { 1559 bits<5> Rs; 1560 bits<2> Pu; 1561 let isPredicated = isPred; 1562 let isPredicatedFalse = isPredNot; 1563 1564 let IClass = 0b0101; 1565 let Inst{27-25} = 0b000; 1566 let Inst{24-23} = !if (isPred, 0b10, 0b01); 1567 let Inst{22} = 0; 1568 let Inst{21} = isPredNot; 1569 let Inst{9-8} = !if (isPred, Pu, 0b00); 1570 let Inst{20-16} = Rs; 1571 1572 } 1573 1574let Defs = VolatileV3.Regs in { 1575 def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>; 1576 def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>; 1577} 1578 1579let isTerminator = 1, hasSideEffects = 0 in { 1580 defm J2_jump : JMP_base<"JMP", "">, PredNewRel; 1581 1582 // Deal with explicit assembly 1583 // - never extened a jump #, always extend a jump ## 1584 let isAsmParserOnly = 1 in { 1585 defm J2_jump_ext : JMP_base<"JMP", "##">; 1586 defm J2_jump_noext : JMP_base<"JMP", "#">; 1587 } 1588 1589 defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel; 1590 1591 let isReturn = 1, isCodeGenOnly = 1 in 1592 defm JMPret : JMPR_base<"JMPret">, PredNewRel; 1593} 1594 1595def: Pat<(br bb:$dst), 1596 (J2_jump brtarget:$dst)>; 1597def: Pat<(retflag), 1598 (JMPret (i32 R31))>; 1599def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset), 1600 (J2_jumpt PredRegs:$src1, bb:$offset)>; 1601 1602// A return through builtin_eh_return. 1603let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, 1604 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 1605def EH_RETURN_JMPR : T_JMPr; 1606 1607def: Pat<(eh_return), 1608 (EH_RETURN_JMPR (i32 R31))>; 1609def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)), 1610 (J2_jumpr IntRegs:$dst)>; 1611def: Pat<(brind (i32 IntRegs:$dst)), 1612 (J2_jumpr IntRegs:$dst)>; 1613 1614//===----------------------------------------------------------------------===// 1615// JR - 1616//===----------------------------------------------------------------------===// 1617 1618//===----------------------------------------------------------------------===// 1619// LD + 1620//===----------------------------------------------------------------------===// 1621 1622// Load - Base with Immediate offset addressing mode 1623let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in 1624class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp, 1625 Operand ImmOp> 1626 : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset), 1627 "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel { 1628 bits<4> name; 1629 bits<5> dst; 1630 bits<5> src1; 1631 bits<14> offset; 1632 bits<11> offsetBits; 1633 1634 string ImmOpStr = !cast<string>(ImmOp); 1635 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3}, 1636 !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2}, 1637 !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1}, 1638 /* s11_0Ext */ offset{10-0}))); 1639 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, 1640 !if (!eq(ImmOpStr, "s11_2Ext"), 13, 1641 !if (!eq(ImmOpStr, "s11_1Ext"), 12, 1642 /* s11_0Ext */ 11))); 1643 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 1644 1645 let IClass = 0b1001; 1646 1647 let Inst{27} = 0b0; 1648 let Inst{26-25} = offsetBits{10-9}; 1649 let Inst{24-21} = MajOp; 1650 let Inst{20-16} = src1; 1651 let Inst{13-5} = offsetBits{8-0}; 1652 let Inst{4-0} = dst; 1653 } 1654 1655let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in 1656class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp, 1657 Operand ImmOp, bit isNot, bit isPredNew> 1658 : LDInst<(outs RC:$dst), 1659 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1660 "if ("#!if(isNot, "!$src1", "$src1") 1661 #!if(isPredNew, ".new", "") 1662 #") $dst = "#mnemonic#"($src2 + #$offset)", 1663 [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel { 1664 bits<5> dst; 1665 bits<2> src1; 1666 bits<5> src2; 1667 bits<9> offset; 1668 bits<6> offsetBits; 1669 string ImmOpStr = !cast<string>(ImmOp); 1670 1671 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3}, 1672 !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2}, 1673 !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1}, 1674 /* u6_0Ext */ offset{5-0}))); 1675 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, 1676 !if (!eq(ImmOpStr, "u6_2Ext"), 8, 1677 !if (!eq(ImmOpStr, "u6_1Ext"), 7, 1678 /* u6_0Ext */ 6))); 1679 let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1); 1680 let isPredicatedNew = isPredNew; 1681 let isPredicatedFalse = isNot; 1682 1683 let IClass = 0b0100; 1684 1685 let Inst{27} = 0b0; 1686 let Inst{27} = 0b0; 1687 let Inst{26} = isNot; 1688 let Inst{25} = isPredNew; 1689 let Inst{24-21} = MajOp; 1690 let Inst{20-16} = src2; 1691 let Inst{13} = 0b0; 1692 let Inst{12-11} = src1; 1693 let Inst{10-5} = offsetBits; 1694 let Inst{4-0} = dst; 1695 } 1696 1697let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in 1698multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC, 1699 Operand ImmOp, Operand predImmOp, bits<4>MajOp> { 1700 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { 1701 let isPredicable = 1 in 1702 def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>; 1703 1704 // Predicated 1705 def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>; 1706 def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>; 1707 1708 // Predicated new 1709 def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>; 1710 def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>; 1711 } 1712} 1713 1714let accessSize = ByteAccess in { 1715 defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>; 1716 defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; 1717} 1718 1719let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1720 defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>; 1721 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>; 1722} 1723 1724let accessSize = WordAccess, opExtentAlign = 2 in 1725defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>; 1726 1727let accessSize = DoubleWordAccess, opExtentAlign = 3 in 1728defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>; 1729 1730let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1731 def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>; 1732 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>; 1733} 1734 1735let accessSize = WordAccess, opExtentAlign = 2 in { 1736 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>; 1737 def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>; 1738} 1739 1740let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0, 1741 opExtendable = 3, isExtentSigned = 1 in 1742class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp> 1743 : LDInst<(outs DoubleRegs:$dst), 1744 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1745 "$dst = "#str#"($src2 + #$offset)", [], 1746 "$src1 = $dst">, AddrModeRel { 1747 bits<4> name; 1748 bits<5> dst; 1749 bits<5> src2; 1750 bits<12> offset; 1751 bits<11> offsetBits; 1752 1753 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1}, 1754 /* s11_0Ext */ offset{10-0}); 1755 let IClass = 0b1001; 1756 1757 let Inst{27} = 0b0; 1758 let Inst{26-25} = offsetBits{10-9}; 1759 let Inst{24-21} = MajOp; 1760 let Inst{20-16} = src2; 1761 let Inst{13-5} = offsetBits{8-0}; 1762 let Inst{4-0} = dst; 1763 } 1764 1765let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in 1766def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>; 1767 1768let accessSize = ByteAccess, opExtentBits = 11 in 1769def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>; 1770 1771// Patterns to select load-indexed (i.e. load from base+offset). 1772multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, 1773 InstHexagon MI> { 1774 def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; 1775 def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))), 1776 (VT (MI AddrFI:$fi, imm:$Off))>; 1777 def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))), 1778 (VT (MI IntRegs:$Rs, imm:$Off))>; 1779 def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>; 1780} 1781 1782let AddedComplexity = 20 in { 1783 defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>; 1784 defm: Loadx_pat<load, i64, s29_3ImmPred, L2_loadrd_io>; 1785 defm: Loadx_pat<atomic_load_8 , i32, s32_0ImmPred, L2_loadrub_io>; 1786 defm: Loadx_pat<atomic_load_16, i32, s31_1ImmPred, L2_loadruh_io>; 1787 defm: Loadx_pat<atomic_load_32, i32, s30_2ImmPred, L2_loadri_io>; 1788 defm: Loadx_pat<atomic_load_64, i64, s29_3ImmPred, L2_loadrd_io>; 1789 1790 defm: Loadx_pat<extloadi1, i32, s32_0ImmPred, L2_loadrub_io>; 1791 defm: Loadx_pat<extloadi8, i32, s32_0ImmPred, L2_loadrub_io>; 1792 defm: Loadx_pat<extloadi16, i32, s31_1ImmPred, L2_loadruh_io>; 1793 defm: Loadx_pat<sextloadi8, i32, s32_0ImmPred, L2_loadrb_io>; 1794 defm: Loadx_pat<sextloadi16, i32, s31_1ImmPred, L2_loadrh_io>; 1795 defm: Loadx_pat<zextloadi1, i32, s32_0ImmPred, L2_loadrub_io>; 1796 defm: Loadx_pat<zextloadi8, i32, s32_0ImmPred, L2_loadrub_io>; 1797 defm: Loadx_pat<zextloadi16, i32, s31_1ImmPred, L2_loadruh_io>; 1798 // No sextloadi1. 1799} 1800 1801// Sign-extending loads of i1 need to replicate the lowest bit throughout 1802// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should 1803// do the trick. 1804let AddedComplexity = 20 in 1805def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))), 1806 (A2_subri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; 1807 1808//===----------------------------------------------------------------------===// 1809// Post increment load 1810//===----------------------------------------------------------------------===// 1811//===----------------------------------------------------------------------===// 1812// Template class for non-predicated post increment loads with immediate offset. 1813//===----------------------------------------------------------------------===// 1814let hasSideEffects = 0, addrMode = PostInc in 1815class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 1816 bits<4> MajOp > 1817 : LDInstPI <(outs RC:$dst, IntRegs:$dst2), 1818 (ins IntRegs:$src1, ImmOp:$offset), 1819 "$dst = "#mnemonic#"($src1++#$offset)" , 1820 [], 1821 "$src1 = $dst2" > , 1822 PredNewRel { 1823 bits<5> dst; 1824 bits<5> src1; 1825 bits<7> offset; 1826 bits<4> offsetBits; 1827 1828 string ImmOpStr = !cast<string>(ImmOp); 1829 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 1830 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 1831 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 1832 /* s4_0Imm */ offset{3-0}))); 1833 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 1834 1835 let IClass = 0b1001; 1836 1837 let Inst{27-25} = 0b101; 1838 let Inst{24-21} = MajOp; 1839 let Inst{20-16} = src1; 1840 let Inst{13-12} = 0b00; 1841 let Inst{8-5} = offsetBits; 1842 let Inst{4-0} = dst; 1843 } 1844 1845//===----------------------------------------------------------------------===// 1846// Template class for predicated post increment loads with immediate offset. 1847//===----------------------------------------------------------------------===// 1848let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in 1849class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 1850 bits<4> MajOp, bit isPredNot, bit isPredNew > 1851 : LDInst <(outs RC:$dst, IntRegs:$dst2), 1852 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1853 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 1854 ") ")#"$dst = "#mnemonic#"($src2++#$offset)", 1855 [] , 1856 "$src2 = $dst2" > , 1857 PredNewRel { 1858 bits<5> dst; 1859 bits<2> src1; 1860 bits<5> src2; 1861 bits<7> offset; 1862 bits<4> offsetBits; 1863 1864 let isPredicatedNew = isPredNew; 1865 let isPredicatedFalse = isPredNot; 1866 1867 string ImmOpStr = !cast<string>(ImmOp); 1868 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 1869 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 1870 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 1871 /* s4_0Imm */ offset{3-0}))); 1872 let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 1873 1874 let IClass = 0b1001; 1875 1876 let Inst{27-25} = 0b101; 1877 let Inst{24-21} = MajOp; 1878 let Inst{20-16} = src2; 1879 let Inst{13} = 0b1; 1880 let Inst{12} = isPredNew; 1881 let Inst{11} = isPredNot; 1882 let Inst{10-9} = src1; 1883 let Inst{8-5} = offsetBits; 1884 let Inst{4-0} = dst; 1885 } 1886 1887//===----------------------------------------------------------------------===// 1888// Multiclass for post increment loads with immediate offset. 1889//===----------------------------------------------------------------------===// 1890 1891multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, 1892 Operand ImmOp, bits<4> MajOp> { 1893 let BaseOpcode = "POST_"#BaseOp in { 1894 let isPredicable = 1 in 1895 def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>; 1896 1897 // Predicated 1898 def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>; 1899 def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>; 1900 1901 // Predicated new 1902 def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>; 1903 def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>; 1904 } 1905} 1906 1907// post increment byte loads with immediate offset 1908let accessSize = ByteAccess in { 1909 defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; 1910 defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; 1911} 1912 1913// post increment halfword loads with immediate offset 1914let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1915 defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>; 1916 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>; 1917} 1918 1919// post increment word loads with immediate offset 1920let accessSize = WordAccess, opExtentAlign = 2 in 1921defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>; 1922 1923// post increment doubleword loads with immediate offset 1924let accessSize = DoubleWordAccess, opExtentAlign = 3 in 1925defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; 1926 1927// Rd=memb[u]h(Rx++#s4:1) 1928// Rdd=memb[u]h(Rx++#s4:2) 1929let accessSize = HalfWordAccess, opExtentAlign = 1 in { 1930 def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>; 1931 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>; 1932} 1933let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in { 1934 def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>; 1935 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>; 1936} 1937 1938//===----------------------------------------------------------------------===// 1939// Template class for post increment fifo loads with immediate offset. 1940//===----------------------------------------------------------------------===// 1941let hasSideEffects = 0, addrMode = PostInc in 1942class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp > 1943 : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2), 1944 (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), 1945 "$dst = "#mnemonic#"($src2++#$offset)" , 1946 [], "$src2 = $dst2, $src1 = $dst" > , 1947 PredNewRel { 1948 bits<5> dst; 1949 bits<5> src2; 1950 bits<5> offset; 1951 bits<4> offsetBits; 1952 1953 let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1}, 1954 /* s4_0Imm */ offset{3-0}); 1955 let IClass = 0b1001; 1956 1957 let Inst{27-25} = 0b101; 1958 let Inst{24-21} = MajOp; 1959 let Inst{20-16} = src2; 1960 let Inst{13-12} = 0b00; 1961 let Inst{8-5} = offsetBits; 1962 let Inst{4-0} = dst; 1963 } 1964 1965// Ryy=memh_fifo(Rx++#s4:1) 1966// Ryy=memb_fifo(Rx++#s4:0) 1967let accessSize = ByteAccess in 1968def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>; 1969 1970let accessSize = HalfWordAccess, opExtentAlign = 1 in 1971def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>; 1972 1973//===----------------------------------------------------------------------===// 1974// Template class for post increment loads with register offset. 1975//===----------------------------------------------------------------------===// 1976let hasSideEffects = 0, addrMode = PostInc in 1977class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp, 1978 MemAccessSize AccessSz> 1979 : LDInstPI <(outs RC:$dst, IntRegs:$_dst_), 1980 (ins IntRegs:$src1, ModRegs:$src2), 1981 "$dst = "#mnemonic#"($src1++$src2)" , 1982 [], "$src1 = $_dst_" > { 1983 bits<5> dst; 1984 bits<5> src1; 1985 bits<1> src2; 1986 1987 let accessSize = AccessSz; 1988 let IClass = 0b1001; 1989 1990 let Inst{27-25} = 0b110; 1991 let Inst{24-21} = MajOp; 1992 let Inst{20-16} = src1; 1993 let Inst{13} = src2; 1994 let Inst{12} = 0b0; 1995 let Inst{7} = 0b0; 1996 let Inst{4-0} = dst; 1997 } 1998 1999let hasNewValue = 1 in { 2000 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>; 2001 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>; 2002 def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>; 2003 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>; 2004 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>; 2005 2006 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>; 2007} 2008 2009def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>; 2010def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>; 2011 2012// Load predicate. 2013let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, 2014 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 2015def LDriw_pred : LDInst<(outs PredRegs:$dst), 2016 (ins IntRegs:$addr, s11_2Ext:$off), 2017 ".error \"should not emit\"", []>; 2018 2019let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in 2020 def L2_deallocframe : LDInst<(outs), (ins), 2021 "deallocframe", 2022 []> { 2023 let IClass = 0b1001; 2024 2025 let Inst{27-16} = 0b000000011110; 2026 let Inst{13} = 0b0; 2027 let Inst{4-0} = 0b11110; 2028} 2029 2030// Load / Post increment circular addressing mode. 2031let Uses = [CS], hasSideEffects = 0 in 2032class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp> 2033 : LDInst <(outs RC:$dst, IntRegs:$_dst_), 2034 (ins IntRegs:$Rz, ModRegs:$Mu), 2035 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], 2036 "$Rz = $_dst_" > { 2037 bits<5> dst; 2038 bits<5> Rz; 2039 bit Mu; 2040 2041 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 2042 let IClass = 0b1001; 2043 2044 let Inst{27-25} = 0b100; 2045 let Inst{24-21} = MajOp; 2046 let Inst{20-16} = Rz; 2047 let Inst{13} = Mu; 2048 let Inst{12} = 0b0; 2049 let Inst{9} = 0b1; 2050 let Inst{7} = 0b0; 2051 let Inst{4-0} = dst; 2052 } 2053 2054let accessSize = ByteAccess in { 2055 def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>; 2056 def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>; 2057} 2058 2059let accessSize = HalfWordAccess in { 2060 def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>; 2061 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>; 2062 def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>; 2063 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>; 2064} 2065 2066let accessSize = WordAccess in { 2067 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>; 2068 let hasNewValue = 0 in { 2069 def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>; 2070 def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>; 2071 } 2072} 2073 2074let accessSize = DoubleWordAccess in 2075def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>; 2076 2077// Load / Post increment circular addressing mode. 2078let Uses = [CS], hasSideEffects = 0 in 2079class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz > 2080 : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_), 2081 (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu), 2082 "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], 2083 "$Rz = $_dst_, $dst = $_src_" > { 2084 bits<5> dst; 2085 bits<5> Rz; 2086 bit Mu; 2087 2088 let accessSize = AccessSz; 2089 let IClass = 0b1001; 2090 2091 let Inst{27-25} = 0b100; 2092 let Inst{24-21} = MajOp; 2093 let Inst{20-16} = Rz; 2094 let Inst{13} = Mu; 2095 let Inst{12} = 0b0; 2096 let Inst{9} = 0b1; 2097 let Inst{7} = 0b0; 2098 let Inst{4-0} = dst; 2099 } 2100 2101def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>; 2102def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>; 2103 2104//===----------------------------------------------------------------------===// 2105// Circular loads with immediate offset. 2106//===----------------------------------------------------------------------===// 2107let Uses = [CS], mayLoad = 1, hasSideEffects = 0 in 2108class T_load_pci <string mnemonic, RegisterClass RC, 2109 Operand ImmOp, bits<4> MajOp> 2110 : LDInstPI<(outs RC:$dst, IntRegs:$_dst_), 2111 (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu), 2112 "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [], 2113 "$Rz = $_dst_"> { 2114 bits<5> dst; 2115 bits<5> Rz; 2116 bits<1> Mu; 2117 bits<7> offset; 2118 bits<4> offsetBits; 2119 2120 string ImmOpStr = !cast<string>(ImmOp); 2121 let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); 2122 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 2123 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 2124 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 2125 /* s4_0Imm */ offset{3-0}))); 2126 let IClass = 0b1001; 2127 let Inst{27-25} = 0b100; 2128 let Inst{24-21} = MajOp; 2129 let Inst{20-16} = Rz; 2130 let Inst{13} = Mu; 2131 let Inst{12} = 0b0; 2132 let Inst{9} = 0b0; 2133 let Inst{8-5} = offsetBits; 2134 let Inst{4-0} = dst; 2135 } 2136 2137// Byte variants of circ load 2138let accessSize = ByteAccess in { 2139 def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>; 2140 def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>; 2141} 2142 2143// Half word variants of circ load 2144let accessSize = HalfWordAccess in { 2145 def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>; 2146 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>; 2147 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>; 2148 def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>; 2149} 2150 2151// Word variants of circ load 2152let accessSize = WordAccess in 2153def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>; 2154 2155let accessSize = WordAccess, hasNewValue = 0 in { 2156 def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>; 2157 def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>; 2158} 2159 2160let accessSize = DoubleWordAccess, hasNewValue = 0 in 2161def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>; 2162 2163//===----------------------------------------------------------------------===// 2164// Circular loads - Pseudo 2165// 2166// Please note that the input operand order in the pseudo instructions 2167// doesn't match with the real instructions. Pseudo instructions operand 2168// order should mimics the ordering in the intrinsics. Also, 'src2' doesn't 2169// appear in the AsmString because it's same as 'dst'. 2170//===----------------------------------------------------------------------===// 2171let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in 2172class T_load_pci_pseudo <string opc, RegisterClass RC> 2173 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst), 2174 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4Imm:$src4), 2175 ".error \"$dst = "#opc#"($src1++#$src4:circ($src3))\"", 2176 [], "$src1 = $_dst_">; 2177 2178def L2_loadrb_pci_pseudo : T_load_pci_pseudo <"memb", IntRegs>; 2179def L2_loadrub_pci_pseudo : T_load_pci_pseudo <"memub", IntRegs>; 2180def L2_loadrh_pci_pseudo : T_load_pci_pseudo <"memh", IntRegs>; 2181def L2_loadruh_pci_pseudo : T_load_pci_pseudo <"memuh", IntRegs>; 2182def L2_loadri_pci_pseudo : T_load_pci_pseudo <"memw", IntRegs>; 2183def L2_loadrd_pci_pseudo : T_load_pci_pseudo <"memd", DoubleRegs>; 2184 2185 2186// TODO: memb_fifo and memh_fifo must take destination register as input. 2187// One-off circ loads - not enough in common to break into a class. 2188let accessSize = ByteAccess in 2189def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>; 2190 2191let accessSize = HalfWordAccess, opExtentAlign = 1 in 2192def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>; 2193 2194// L[24]_load[wd]_locked: Load word/double with lock. 2195let isSoloAX = 1 in 2196class T_load_locked <string mnemonic, RegisterClass RC> 2197 : LD0Inst <(outs RC:$dst), 2198 (ins IntRegs:$src), 2199 "$dst = "#mnemonic#"($src)"> { 2200 bits<5> dst; 2201 bits<5> src; 2202 let IClass = 0b1001; 2203 let Inst{27-21} = 0b0010000; 2204 let Inst{20-16} = src; 2205 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00); 2206 let Inst{5} = 0; 2207 let Inst{4-0} = dst; 2208} 2209let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in 2210 def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>; 2211let accessSize = DoubleWordAccess in 2212 def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>; 2213 2214// S[24]_store[wd]_locked: Store word/double conditionally. 2215let isSoloAX = 1, isPredicateLate = 1 in 2216class T_store_locked <string mnemonic, RegisterClass RC> 2217 : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt), 2218 mnemonic#"($Rs, $Pd) = $Rt"> { 2219 bits<2> Pd; 2220 bits<5> Rs; 2221 bits<5> Rt; 2222 2223 let IClass = 0b1010; 2224 let Inst{27-23} = 0b00001; 2225 let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1); 2226 let Inst{21} = 0b1; 2227 let Inst{20-16} = Rs; 2228 let Inst{12-8} = Rt; 2229 let Inst{1-0} = Pd; 2230} 2231 2232let accessSize = WordAccess in 2233def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>; 2234 2235let accessSize = DoubleWordAccess in 2236def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>; 2237 2238//===----------------------------------------------------------------------===// 2239// Bit-reversed loads with auto-increment register 2240//===----------------------------------------------------------------------===// 2241let hasSideEffects = 0 in 2242class T_load_pbr<string mnemonic, RegisterClass RC, 2243 MemAccessSize addrSize, bits<4> majOp> 2244 : LDInst 2245 <(outs RC:$dst, IntRegs:$_dst_), 2246 (ins IntRegs:$Rz, ModRegs:$Mu), 2247 "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" , 2248 [] , "$Rz = $_dst_" > { 2249 2250 let accessSize = addrSize; 2251 2252 bits<5> dst; 2253 bits<5> Rz; 2254 bits<1> Mu; 2255 2256 let IClass = 0b1001; 2257 2258 let Inst{27-25} = 0b111; 2259 let Inst{24-21} = majOp; 2260 let Inst{20-16} = Rz; 2261 let Inst{13} = Mu; 2262 let Inst{12} = 0b0; 2263 let Inst{7} = 0b0; 2264 let Inst{4-0} = dst; 2265 } 2266 2267let hasNewValue =1, opNewValue = 0 in { 2268 def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>; 2269 def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>; 2270 def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>; 2271 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>; 2272 def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>; 2273 def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>; 2274 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>; 2275} 2276 2277def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>; 2278def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>; 2279def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>; 2280 2281def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>; 2282def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs, 2283 HalfWordAccess, 0b0010>; 2284 2285//===----------------------------------------------------------------------===// 2286// Bit-reversed loads - Pseudo 2287// 2288// Please note that 'src2' doesn't appear in the AsmString because 2289// it's same as 'dst'. 2290//===----------------------------------------------------------------------===// 2291let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in 2292class T_load_pbr_pseudo <string opc, RegisterClass RC> 2293 : LDInstPI<(outs IntRegs:$_dst_, RC:$dst), 2294 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), 2295 ".error \"$dst = "#opc#"($src1++$src3:brev)\"", 2296 [], "$src1 = $_dst_">; 2297 2298def L2_loadrb_pbr_pseudo : T_load_pbr_pseudo <"memb", IntRegs>; 2299def L2_loadrub_pbr_pseudo : T_load_pbr_pseudo <"memub", IntRegs>; 2300def L2_loadrh_pbr_pseudo : T_load_pbr_pseudo <"memh", IntRegs>; 2301def L2_loadruh_pbr_pseudo : T_load_pbr_pseudo <"memuh", IntRegs>; 2302def L2_loadri_pbr_pseudo : T_load_pbr_pseudo <"memw", IntRegs>; 2303def L2_loadrd_pbr_pseudo : T_load_pbr_pseudo <"memd", DoubleRegs>; 2304 2305//===----------------------------------------------------------------------===// 2306// LD - 2307//===----------------------------------------------------------------------===// 2308 2309//===----------------------------------------------------------------------===// 2310// MTYPE/ALU + 2311//===----------------------------------------------------------------------===// 2312//===----------------------------------------------------------------------===// 2313// MTYPE/ALU - 2314//===----------------------------------------------------------------------===// 2315 2316//===----------------------------------------------------------------------===// 2317// MTYPE/COMPLEX + 2318//===----------------------------------------------------------------------===// 2319//===----------------------------------------------------------------------===// 2320// MTYPE/COMPLEX - 2321//===----------------------------------------------------------------------===// 2322 2323//===----------------------------------------------------------------------===// 2324// MTYPE/MPYH + 2325//===----------------------------------------------------------------------===// 2326 2327//===----------------------------------------------------------------------===// 2328// Template Class 2329// MPYS / Multipy signed/unsigned halfwords 2330//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 2331//===----------------------------------------------------------------------===// 2332 2333let hasNewValue = 1, opNewValue = 0 in 2334class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd, 2335 bit hasShift, bit isUnsigned> 2336 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 2337 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") 2338 #", $Rt."#!if(LHbits{0},"h)","l)") 2339 #!if(hasShift,":<<1","") 2340 #!if(isRnd,":rnd","") 2341 #!if(isSat,":sat",""), 2342 [], "", M_tc_3x_SLOT23 > { 2343 bits<5> Rd; 2344 bits<5> Rs; 2345 bits<5> Rt; 2346 2347 let IClass = 0b1110; 2348 2349 let Inst{27-24} = 0b1100; 2350 let Inst{23} = hasShift; 2351 let Inst{22} = isUnsigned; 2352 let Inst{21} = isRnd; 2353 let Inst{7} = isSat; 2354 let Inst{6-5} = LHbits; 2355 let Inst{4-0} = Rd; 2356 let Inst{20-16} = Rs; 2357 let Inst{12-8} = Rt; 2358 } 2359 2360//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2361def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>; 2362def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>; 2363def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>; 2364def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>; 2365def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>; 2366def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>; 2367def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>; 2368def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>; 2369 2370//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2371def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>; 2372def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>; 2373def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>; 2374def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>; 2375def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>; 2376def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>; 2377def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>; 2378def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>; 2379 2380//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd 2381def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>; 2382def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>; 2383def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>; 2384def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>; 2385def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>; 2386def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>; 2387def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>; 2388def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>; 2389 2390//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2391//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] 2392let Defs = [USR_OVF] in { 2393 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>; 2394 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>; 2395 def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>; 2396 def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>; 2397 def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>; 2398 def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>; 2399 def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>; 2400 def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>; 2401 2402 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>; 2403 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>; 2404 def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>; 2405 def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>; 2406 def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>; 2407 def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>; 2408 def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>; 2409 def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>; 2410} 2411 2412//===----------------------------------------------------------------------===// 2413// Template Class 2414// MPYS / Multipy signed/unsigned halfwords and add/subtract the 2415// result from the accumulator. 2416//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2417//===----------------------------------------------------------------------===// 2418 2419let hasNewValue = 1, opNewValue = 0 in 2420class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac, 2421 bit hasShift, bit isUnsigned > 2422 : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 2423 "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") 2424 #"($Rs."#!if(LHbits{1},"h","l") 2425 #", $Rt."#!if(LHbits{0},"h)","l)") 2426 #!if(hasShift,":<<1","") 2427 #!if(isSat,":sat",""), 2428 [], "$dst2 = $Rx", M_tc_3x_SLOT23 > { 2429 bits<5> Rx; 2430 bits<5> Rs; 2431 bits<5> Rt; 2432 2433 let IClass = 0b1110; 2434 let Inst{27-24} = 0b1110; 2435 let Inst{23} = hasShift; 2436 let Inst{22} = isUnsigned; 2437 let Inst{21} = isNac; 2438 let Inst{7} = isSat; 2439 let Inst{6-5} = LHbits; 2440 let Inst{4-0} = Rx; 2441 let Inst{20-16} = Rs; 2442 let Inst{12-8} = Rt; 2443 } 2444 2445//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2446def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>; 2447def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>; 2448def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>; 2449def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>; 2450def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>; 2451def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>; 2452def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>; 2453def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>; 2454 2455//Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2456def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>; 2457def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>; 2458def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>; 2459def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>; 2460def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>; 2461def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>; 2462def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>; 2463def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>; 2464 2465//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1] 2466def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>; 2467def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>; 2468def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>; 2469def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>; 2470def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>; 2471def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>; 2472def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>; 2473def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>; 2474 2475//Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1] 2476def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>; 2477def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>; 2478def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>; 2479def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>; 2480def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>; 2481def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>; 2482def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>; 2483def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>; 2484 2485//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat 2486def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>; 2487def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>; 2488def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>; 2489def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>; 2490def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>; 2491def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>; 2492def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>; 2493def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>; 2494 2495//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat 2496def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>; 2497def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>; 2498def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>; 2499def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>; 2500def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>; 2501def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>; 2502def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>; 2503def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>; 2504 2505//===----------------------------------------------------------------------===// 2506// Template Class 2507// MPYS / Multipy signed/unsigned halfwords and add/subtract the 2508// result from the 64-bit destination register. 2509//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] 2510//===----------------------------------------------------------------------===// 2511 2512class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned> 2513 : MInst_acc<(outs DoubleRegs:$Rxx), 2514 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 2515 "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") 2516 #"($Rs."#!if(LHbits{1},"h","l") 2517 #", $Rt."#!if(LHbits{0},"h)","l)") 2518 #!if(hasShift,":<<1",""), 2519 [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > { 2520 bits<5> Rxx; 2521 bits<5> Rs; 2522 bits<5> Rt; 2523 2524 let IClass = 0b1110; 2525 2526 let Inst{27-24} = 0b0110; 2527 let Inst{23} = hasShift; 2528 let Inst{22} = isUnsigned; 2529 let Inst{21} = isNac; 2530 let Inst{7} = 0; 2531 let Inst{6-5} = LHbits; 2532 let Inst{4-0} = Rxx; 2533 let Inst{20-16} = Rs; 2534 let Inst{12-8} = Rt; 2535 } 2536 2537def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>; 2538def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>; 2539def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>; 2540def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>; 2541 2542def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>; 2543def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>; 2544def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>; 2545def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>; 2546 2547def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>; 2548def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>; 2549def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>; 2550def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>; 2551 2552def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>; 2553def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>; 2554def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>; 2555def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>; 2556 2557def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>; 2558def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>; 2559def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>; 2560def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>; 2561 2562def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>; 2563def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>; 2564def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>; 2565def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>; 2566 2567def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>; 2568def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>; 2569def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>; 2570def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>; 2571 2572def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>; 2573def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>; 2574def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>; 2575def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>; 2576 2577//===----------------------------------------------------------------------===// 2578// Template Class -- Vector Multipy 2579// Used for complex multiply real or imaginary, dual multiply and even halfwords 2580//===----------------------------------------------------------------------===// 2581class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, 2582 bit isRnd, bit isSat > 2583 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 2584 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2585 #!if(isRnd,":rnd","") 2586 #!if(isSat,":sat",""), 2587 [] > { 2588 bits<5> Rdd; 2589 bits<5> Rss; 2590 bits<5> Rtt; 2591 2592 let IClass = 0b1110; 2593 2594 let Inst{27-24} = 0b1000; 2595 let Inst{23-21} = MajOp; 2596 let Inst{7-5} = MinOp; 2597 let Inst{4-0} = Rdd; 2598 let Inst{20-16} = Rss; 2599 let Inst{12-8} = Rtt; 2600 } 2601 2602// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat 2603let Defs = [USR_OVF] in { 2604def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>; 2605def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>; 2606 2607// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat 2608def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>; 2609def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>; 2610 2611// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat 2612def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>; 2613def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>; 2614 2615// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat 2616def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>; 2617def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>; 2618 2619//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat 2620def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>; 2621def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>; 2622def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>; 2623def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>; 2624 2625//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat 2626def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>; 2627def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>; 2628def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>; 2629def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>; 2630 2631//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat 2632def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>; 2633def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>; 2634def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>; 2635def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>; 2636 2637//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat 2638def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>; 2639def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>; 2640def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>; 2641def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>; 2642} 2643 2644let hasNewValue = 1, opNewValue = 0 in 2645class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC, 2646 bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0, 2647 string op2Suffix = "", bit isRaw = 0, bit isHi = 0 > 2648 : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2), 2649 "$dst = "#mnemonic 2650 #"($src1, $src2"#op2Suffix#")" 2651 #!if(MajOp{2}, ":<<1", "") 2652 #!if(isRnd, ":rnd", "") 2653 #!if(isSat, ":sat", "") 2654 #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > { 2655 bits<5> dst; 2656 bits<5> src1; 2657 bits<5> src2; 2658 2659 let IClass = 0b1110; 2660 2661 let Inst{27-24} = RegTyBits; 2662 let Inst{23-21} = MajOp; 2663 let Inst{20-16} = src1; 2664 let Inst{13} = 0b0; 2665 let Inst{12-8} = src2; 2666 let Inst{7-5} = MinOp; 2667 let Inst{4-0} = dst; 2668 } 2669 2670class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi> 2671 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>; 2672 2673class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2674 bit isSat = 0, bit isRnd = 0 > 2675 : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>; 2676 2677class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2678 bit isSat = 0, bit isRnd = 0 > 2679 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>; 2680 2681class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2682 bit isSat = 0, bit isRnd = 0, string op2str = "" > 2683 : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>; 2684 2685def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>; 2686def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>; 2687def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>; 2688 2689let CextOpcode = "mpyi", InputType = "reg" in 2690def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel; 2691 2692def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>; 2693def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>; 2694 2695def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>; 2696 2697def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>; 2698def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>; 2699 2700def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">; 2701def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">; 2702 2703def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>; 2704def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>; 2705def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">; 2706def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">; 2707 2708// V4 Instructions 2709def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>; 2710def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>; 2711def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>; 2712def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>; 2713 2714def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">; 2715def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">; 2716 2717def: Pat<(i32 (mul I32:$src1, I32:$src2)), (M2_mpyi I32:$src1, I32:$src2)>; 2718def: Pat<(i32 (mulhs I32:$src1, I32:$src2)), (M2_mpy_up I32:$src1, I32:$src2)>; 2719def: Pat<(i32 (mulhu I32:$src1, I32:$src2)), (M2_mpyu_up I32:$src1, I32:$src2)>; 2720 2721let hasNewValue = 1, opNewValue = 0 in 2722class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern> 2723 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8), 2724 "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" , 2725 pattern, "", M_tc_3x_SLOT23> { 2726 bits<5> Rd; 2727 bits<5> Rs; 2728 bits<8> u8; 2729 2730 let IClass = 0b1110; 2731 2732 let Inst{27-24} = 0b0000; 2733 let Inst{23} = isNeg; 2734 let Inst{13} = 0b0; 2735 let Inst{4-0} = Rd; 2736 let Inst{20-16} = Rs; 2737 let Inst{12-5} = u8; 2738 } 2739 2740let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in 2741def M2_mpysip : T_MType_mpy_ri <0, u8Ext, 2742 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>; 2743 2744def M2_mpysin : T_MType_mpy_ri <1, u8Imm, 2745 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs, 2746 u8ImmPred:$u8)))]>; 2747 2748// Assember mapped to M2_mpyi 2749let isAsmParserOnly = 1 in 2750def M2_mpyui : MInst<(outs IntRegs:$dst), 2751 (ins IntRegs:$src1, IntRegs:$src2), 2752 "$dst = mpyui($src1, $src2)">; 2753 2754// Rd=mpyi(Rs,#m9) 2755// s9 is NOT the same as m9 - but it works.. so far. 2756// Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8) 2757// depending on the value of m9. See Arch Spec. 2758let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9, 2759 CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1, 2760 isAsmParserOnly = 1 in 2761def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2), 2762 "$dst = mpyi($src1, #$src2)", 2763 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1), 2764 s32ImmPred:$src2))]>, ImmRegRel; 2765 2766let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3, 2767 InputType = "imm" in 2768class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp, 2769 list<dag> pattern = []> 2770 : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3), 2771 "$dst "#mnemonic#"($src2, #$src3)", 2772 pattern, "$src1 = $dst", M_tc_2_SLOT23> { 2773 bits<5> dst; 2774 bits<5> src2; 2775 bits<8> src3; 2776 2777 let IClass = 0b1110; 2778 2779 let Inst{27-26} = 0b00; 2780 let Inst{25-23} = MajOp; 2781 let Inst{20-16} = src2; 2782 let Inst{13} = 0b0; 2783 let Inst{12-5} = src3; 2784 let Inst{4-0} = dst; 2785 } 2786 2787let InputType = "reg", hasNewValue = 1 in 2788class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp, 2789 bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0, 2790 bit isSat = 0, bit isShift = 0> 2791 : MInst < (outs IntRegs:$dst), 2792 (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), 2793 "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)") 2794 #!if(isShift, ":<<1", "") 2795 #!if(isSat, ":sat", ""), 2796 pattern, "$src1 = $dst", M_tc_2_SLOT23 > { 2797 bits<5> dst; 2798 bits<5> src2; 2799 bits<5> src3; 2800 2801 let IClass = 0b1110; 2802 2803 let Inst{27-24} = 0b1111; 2804 let Inst{23-21} = MajOp; 2805 let Inst{20-16} = !if(isSwap, src3, src2); 2806 let Inst{13} = 0b0; 2807 let Inst{12-8} = !if(isSwap, src2, src3); 2808 let Inst{7-5} = MinOp; 2809 let Inst{4-0} = dst; 2810 } 2811 2812let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in { 2813 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext, 2814 [(set (i32 IntRegs:$dst), 2815 (add (mul IntRegs:$src2, u32ImmPred:$src3), 2816 IntRegs:$src1))]>, ImmRegRel; 2817 2818 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0, 2819 [(set (i32 IntRegs:$dst), 2820 (add (mul IntRegs:$src2, IntRegs:$src3), 2821 IntRegs:$src1))]>, ImmRegRel; 2822} 2823 2824let CextOpcode = "ADD_acc" in { 2825 let isExtentSigned = 1 in 2826 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext, 2827 [(set (i32 IntRegs:$dst), 2828 (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3), 2829 (i32 IntRegs:$src1)))]>, ImmRegRel; 2830 2831 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, 2832 [(set (i32 IntRegs:$dst), 2833 (add (add (i32 IntRegs:$src2), (i32 IntRegs:$src3)), 2834 (i32 IntRegs:$src1)))]>, ImmRegRel; 2835} 2836 2837let CextOpcode = "SUB_acc" in { 2838 let isExtentSigned = 1 in 2839 def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel; 2840 2841 def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel; 2842} 2843 2844let Itinerary = M_tc_3x_SLOT23 in 2845def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>; 2846 2847def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>; 2848def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>; 2849 2850class T_MType_acc_pat1 <InstHexagon MI, SDNode firstOp, SDNode secOp, 2851 PatLeaf ImmPred> 2852 : Pat <(secOp IntRegs:$src1, (firstOp IntRegs:$src2, ImmPred:$src3)), 2853 (MI IntRegs:$src1, IntRegs:$src2, ImmPred:$src3)>; 2854 2855class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp> 2856 : Pat <(i32 (secOp IntRegs:$src1, (firstOp IntRegs:$src2, IntRegs:$src3))), 2857 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 2858 2859def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>; 2860def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>; 2861 2862def : T_MType_acc_pat1 <M2_naccii, add, sub, s16_16ImmPred>; 2863def : T_MType_acc_pat2 <M2_nacci, add, sub>; 2864 2865//===----------------------------------------------------------------------===// 2866// Template Class -- XType Vector Instructions 2867//===----------------------------------------------------------------------===// 2868class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > 2869 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 2870 "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), 2871 [] > { 2872 bits<5> Rdd; 2873 bits<5> Rss; 2874 bits<5> Rtt; 2875 2876 let IClass = 0b1110; 2877 2878 let Inst{27-24} = 0b1000; 2879 let Inst{23-21} = MajOp; 2880 let Inst{7-5} = MinOp; 2881 let Inst{4-0} = Rdd; 2882 let Inst{20-16} = Rss; 2883 let Inst{12-8} = Rtt; 2884 } 2885 2886class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > 2887 : MInst <(outs DoubleRegs:$Rdd), 2888 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2889 "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), 2890 [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > { 2891 bits<5> Rdd; 2892 bits<5> Rss; 2893 bits<5> Rtt; 2894 2895 let IClass = 0b1110; 2896 2897 let Inst{27-24} = 0b1010; 2898 let Inst{23-21} = MajOp; 2899 let Inst{7-5} = MinOp; 2900 let Inst{4-0} = Rdd; 2901 let Inst{20-16} = Rss; 2902 let Inst{12-8} = Rtt; 2903 } 2904 2905class T_XTYPE_Vect_diff < bits<3> MajOp, string opc > 2906 : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss), 2907 "$Rdd = "#opc#"($Rtt, $Rss)", 2908 [], "",M_tc_2_SLOT23 > { 2909 bits<5> Rdd; 2910 bits<5> Rss; 2911 bits<5> Rtt; 2912 2913 let IClass = 0b1110; 2914 2915 let Inst{27-24} = 0b1000; 2916 let Inst{23-21} = MajOp; 2917 let Inst{7-5} = 0b000; 2918 let Inst{4-0} = Rdd; 2919 let Inst{20-16} = Rss; 2920 let Inst{12-8} = Rtt; 2921 } 2922 2923// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32) 2924def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>; 2925def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>; 2926 2927// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) 2928def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>; 2929def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>; 2930 2931// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) 2932def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">; 2933 2934// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) 2935def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">; 2936 2937// Vector reduce complex multiply real or imaginary: 2938// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) 2939def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>; 2940def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>; 2941def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>; 2942def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>; 2943 2944def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>; 2945def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>; 2946def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>; 2947def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>; 2948 2949// Vector reduce halfwords: 2950// Rdd[+]=vrmpyh(Rss,Rtt) 2951def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>; 2952def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>; 2953 2954//===----------------------------------------------------------------------===// 2955// Template Class -- Vector Multipy with accumulation. 2956// Used for complex multiply real or imaginary, dual multiply and even halfwords 2957//===----------------------------------------------------------------------===// 2958let Defs = [USR_OVF] in 2959class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, 2960 bit hasShift, bit isRnd > 2961 : MInst <(outs DoubleRegs:$Rxx), 2962 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2963 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2964 #!if(isRnd,":rnd","")#":sat", 2965 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { 2966 bits<5> Rxx; 2967 bits<5> Rss; 2968 bits<5> Rtt; 2969 2970 let IClass = 0b1110; 2971 2972 let Inst{27-24} = 0b1010; 2973 let Inst{23-21} = MajOp; 2974 let Inst{7-5} = MinOp; 2975 let Inst{4-0} = Rxx; 2976 let Inst{20-16} = Rss; 2977 let Inst{12-8} = Rtt; 2978 } 2979 2980class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp, 2981 bit hasShift, bit isRnd > 2982 : MInst <(outs DoubleRegs:$Rxx), 2983 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), 2984 "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") 2985 #!if(isRnd,":rnd",""), 2986 [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { 2987 bits<5> Rxx; 2988 bits<5> Rss; 2989 bits<5> Rtt; 2990 2991 let IClass = 0b1110; 2992 2993 let Inst{27-24} = 0b1010; 2994 let Inst{23-21} = MajOp; 2995 let Inst{7-5} = MinOp; 2996 let Inst{4-0} = Rxx; 2997 let Inst{20-16} = Rss; 2998 let Inst{12-8} = Rtt; 2999 } 3000 3001// Vector multiply word by signed half with accumulation 3002// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat 3003def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>; 3004def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>; 3005def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>; 3006def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>; 3007 3008def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>; 3009def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>; 3010def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>; 3011def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>; 3012 3013// Vector multiply word by unsigned half with accumulation 3014// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat 3015def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>; 3016def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>; 3017def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>; 3018def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>; 3019 3020def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>; 3021def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>; 3022def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>; 3023def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>; 3024 3025// Vector multiply even halfwords with accumulation 3026// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] 3027def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>; 3028def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>; 3029def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>; 3030 3031// Vector dual multiply with accumulation 3032// Rxx+=vdmpy(Rss,Rtt)[:sat] 3033def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>; 3034def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>; 3035 3036// Vector complex multiply real or imaginary with accumulation 3037// Rxx+=vcmpy[ir](Rss,Rtt):sat 3038def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>; 3039def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>; 3040 3041//===----------------------------------------------------------------------===// 3042// Template Class -- Multiply signed/unsigned halfwords with and without 3043// saturation and rounding 3044//===----------------------------------------------------------------------===// 3045class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned > 3046 : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt), 3047 "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") 3048 #", $Rt."#!if(LHbits{0},"h)","l)") 3049 #!if(hasShift,":<<1","") 3050 #!if(isRnd,":rnd",""), 3051 [] > { 3052 bits<5> Rdd; 3053 bits<5> Rs; 3054 bits<5> Rt; 3055 3056 let IClass = 0b1110; 3057 3058 let Inst{27-24} = 0b0100; 3059 let Inst{23} = hasShift; 3060 let Inst{22} = isUnsigned; 3061 let Inst{21} = isRnd; 3062 let Inst{6-5} = LHbits; 3063 let Inst{4-0} = Rdd; 3064 let Inst{20-16} = Rs; 3065 let Inst{12-8} = Rt; 3066} 3067 3068def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>; 3069def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>; 3070def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>; 3071def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>; 3072 3073def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>; 3074def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>; 3075def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>; 3076def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>; 3077 3078def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>; 3079def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>; 3080def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>; 3081def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>; 3082 3083def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>; 3084def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>; 3085def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>; 3086def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>; 3087 3088//Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1] 3089def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>; 3090def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>; 3091def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>; 3092def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>; 3093 3094def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>; 3095def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>; 3096def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>; 3097def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>; 3098 3099//===----------------------------------------------------------------------===// 3100// Template Class for xtype mpy: 3101// Vector multiply 3102// Complex multiply 3103// multiply 32X32 and use full result 3104//===----------------------------------------------------------------------===// 3105let hasSideEffects = 0 in 3106class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp, 3107 bit isSat, bit hasShift, bit isConj> 3108 : MInst <(outs DoubleRegs:$Rdd), 3109 (ins IntRegs:$Rs, IntRegs:$Rt), 3110 "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")") 3111 #!if(hasShift,":<<1","") 3112 #!if(isSat,":sat",""), 3113 [] > { 3114 bits<5> Rdd; 3115 bits<5> Rs; 3116 bits<5> Rt; 3117 3118 let IClass = 0b1110; 3119 3120 let Inst{27-24} = 0b0101; 3121 let Inst{23-21} = MajOp; 3122 let Inst{20-16} = Rs; 3123 let Inst{12-8} = Rt; 3124 let Inst{7-5} = MinOp; 3125 let Inst{4-0} = Rdd; 3126 } 3127 3128//===----------------------------------------------------------------------===// 3129// Template Class for xtype mpy with accumulation into 64-bit: 3130// Vector multiply 3131// Complex multiply 3132// multiply 32X32 and use full result 3133//===----------------------------------------------------------------------===// 3134class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp, 3135 bit isSat, bit hasShift, bit isConj> 3136 : MInst <(outs DoubleRegs:$Rxx), 3137 (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), 3138 "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")") 3139 #!if(hasShift,":<<1","") 3140 #!if(isSat,":sat",""), 3141 3142 [] , "$dst2 = $Rxx" > { 3143 bits<5> Rxx; 3144 bits<5> Rs; 3145 bits<5> Rt; 3146 3147 let IClass = 0b1110; 3148 3149 let Inst{27-24} = 0b0111; 3150 let Inst{23-21} = MajOp; 3151 let Inst{20-16} = Rs; 3152 let Inst{12-8} = Rt; 3153 let Inst{7-5} = MinOp; 3154 let Inst{4-0} = Rxx; 3155 } 3156 3157// MPY - Multiply and use full result 3158// Rdd = mpy[u](Rs,Rt) 3159def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>; 3160def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>; 3161 3162// Rxx[+-]= mpy[u](Rs,Rt) 3163def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>; 3164def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>; 3165def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>; 3166def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>; 3167 3168// Complex multiply real or imaginary 3169// Rxx=cmpy[ir](Rs,Rt) 3170def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>; 3171def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>; 3172 3173// Rxx+=cmpy[ir](Rs,Rt) 3174def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>; 3175def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>; 3176 3177// Complex multiply 3178// Rdd=cmpy(Rs,Rt)[:<<]:sat 3179def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>; 3180def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>; 3181 3182// Rdd=cmpy(Rs,Rt*)[:<<]:sat 3183def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>; 3184def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>; 3185 3186// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat 3187def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>; 3188def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>; 3189def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>; 3190def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>; 3191 3192// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat 3193def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>; 3194def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>; 3195def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>; 3196def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>; 3197 3198// Vector multiply halfwords 3199// Rdd=vmpyh(Rs,Rt)[:<<]:sat 3200//let Defs = [USR_OVF] in { 3201 def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>; 3202 def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>; 3203//} 3204 3205// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] 3206def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>; 3207def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>; 3208def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>; 3209 3210def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))), 3211 (i64 (anyext (i32 IntRegs:$src2))))), 3212 (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>; 3213 3214def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))), 3215 (i64 (sext (i32 IntRegs:$src2))))), 3216 (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>; 3217 3218def: Pat<(i64 (mul (is_sext_i32:$src1), 3219 (is_sext_i32:$src2))), 3220 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>; 3221 3222// Multiply and accumulate, use full result. 3223// Rxx[+-]=mpy(Rs,Rt) 3224 3225def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3226 (mul (i64 (sext (i32 IntRegs:$src2))), 3227 (i64 (sext (i32 IntRegs:$src3)))))), 3228 (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3229 3230def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3231 (mul (i64 (sext (i32 IntRegs:$src2))), 3232 (i64 (sext (i32 IntRegs:$src3)))))), 3233 (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3234 3235def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3236 (mul (i64 (anyext (i32 IntRegs:$src2))), 3237 (i64 (anyext (i32 IntRegs:$src3)))))), 3238 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3239 3240def: Pat<(i64 (add (i64 DoubleRegs:$src1), 3241 (mul (i64 (zext (i32 IntRegs:$src2))), 3242 (i64 (zext (i32 IntRegs:$src3)))))), 3243 (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3244 3245def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3246 (mul (i64 (anyext (i32 IntRegs:$src2))), 3247 (i64 (anyext (i32 IntRegs:$src3)))))), 3248 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3249 3250def: Pat<(i64 (sub (i64 DoubleRegs:$src1), 3251 (mul (i64 (zext (i32 IntRegs:$src2))), 3252 (i64 (zext (i32 IntRegs:$src3)))))), 3253 (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>; 3254 3255//===----------------------------------------------------------------------===// 3256// MTYPE/MPYH - 3257//===----------------------------------------------------------------------===// 3258 3259//===----------------------------------------------------------------------===// 3260// MTYPE/MPYS + 3261//===----------------------------------------------------------------------===// 3262//===----------------------------------------------------------------------===// 3263// MTYPE/MPYS - 3264//===----------------------------------------------------------------------===// 3265 3266//===----------------------------------------------------------------------===// 3267// MTYPE/VB + 3268//===----------------------------------------------------------------------===// 3269//===----------------------------------------------------------------------===// 3270// MTYPE/VB - 3271//===----------------------------------------------------------------------===// 3272 3273//===----------------------------------------------------------------------===// 3274// MTYPE/VH + 3275//===----------------------------------------------------------------------===// 3276//===----------------------------------------------------------------------===// 3277// MTYPE/VH - 3278//===----------------------------------------------------------------------===// 3279 3280//===----------------------------------------------------------------------===// 3281// ST + 3282//===----------------------------------------------------------------------===// 3283/// 3284// Store doubleword. 3285//===----------------------------------------------------------------------===// 3286// Template class for non-predicated post increment stores with immediate offset 3287//===----------------------------------------------------------------------===// 3288let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in 3289class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 3290 bits<4> MajOp, bit isHalf > 3291 : STInst <(outs IntRegs:$_dst_), 3292 (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), 3293 mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""), 3294 [], "$src1 = $_dst_" >, 3295 AddrModeRel { 3296 bits<5> src1; 3297 bits<5> src2; 3298 bits<7> offset; 3299 bits<4> offsetBits; 3300 3301 string ImmOpStr = !cast<string>(ImmOp); 3302 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 3303 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 3304 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 3305 /* s4_0Imm */ offset{3-0}))); 3306 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 3307 3308 let IClass = 0b1010; 3309 3310 let Inst{27-25} = 0b101; 3311 let Inst{24-21} = MajOp; 3312 let Inst{20-16} = src1; 3313 let Inst{13} = 0b0; 3314 let Inst{12-8} = src2; 3315 let Inst{7} = 0b0; 3316 let Inst{6-3} = offsetBits; 3317 let Inst{1} = 0b0; 3318 } 3319 3320//===----------------------------------------------------------------------===// 3321// Template class for predicated post increment stores with immediate offset 3322//===----------------------------------------------------------------------===// 3323let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in 3324class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, 3325 bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew > 3326 : STInst <(outs IntRegs:$_dst_), 3327 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), 3328 !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 3329 ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""), 3330 [], "$src2 = $_dst_" >, 3331 AddrModeRel { 3332 bits<2> src1; 3333 bits<5> src2; 3334 bits<7> offset; 3335 bits<5> src3; 3336 bits<4> offsetBits; 3337 3338 string ImmOpStr = !cast<string>(ImmOp); 3339 let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, 3340 !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, 3341 !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, 3342 /* s4_0Imm */ offset{3-0}))); 3343 3344 let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); 3345 let isPredicatedNew = isPredNew; 3346 let isPredicatedFalse = isPredNot; 3347 3348 let IClass = 0b1010; 3349 3350 let Inst{27-25} = 0b101; 3351 let Inst{24-21} = MajOp; 3352 let Inst{20-16} = src2; 3353 let Inst{13} = 0b1; 3354 let Inst{12-8} = src3; 3355 let Inst{7} = isPredNew; 3356 let Inst{6-3} = offsetBits; 3357 let Inst{2} = isPredNot; 3358 let Inst{1-0} = src1; 3359 } 3360 3361multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC, 3362 Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > { 3363 3364 let BaseOpcode = "POST_"#BaseOp in { 3365 def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>; 3366 3367 // Predicated 3368 def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>; 3369 def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>; 3370 3371 // Predicated new 3372 def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, 3373 isHalf, 0, 1>; 3374 def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, 3375 isHalf, 1, 1>; 3376 } 3377} 3378 3379let accessSize = ByteAccess in 3380defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>; 3381 3382let accessSize = HalfWordAccess in 3383defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>; 3384 3385let accessSize = WordAccess in 3386defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>; 3387 3388let accessSize = DoubleWordAccess in 3389defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; 3390 3391let accessSize = HalfWordAccess, isNVStorable = 0 in 3392defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; 3393 3394class Storepi_pat<PatFrag Store, PatFrag Value, PatFrag Offset, 3395 InstHexagon MI> 3396 : Pat<(Store Value:$src1, I32:$src2, Offset:$offset), 3397 (MI I32:$src2, imm:$offset, Value:$src1)>; 3398 3399def: Storepi_pat<post_truncsti8, I32, s4_0ImmPred, S2_storerb_pi>; 3400def: Storepi_pat<post_truncsti16, I32, s4_1ImmPred, S2_storerh_pi>; 3401def: Storepi_pat<post_store, I32, s4_2ImmPred, S2_storeri_pi>; 3402def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; 3403 3404//===----------------------------------------------------------------------===// 3405// Template class for post increment stores with register offset. 3406//===----------------------------------------------------------------------===// 3407let isNVStorable = 1 in 3408class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, 3409 MemAccessSize AccessSz, bit isHalf = 0> 3410 : STInst <(outs IntRegs:$_dst_), 3411 (ins IntRegs:$src1, ModRegs:$src2, RC:$src3), 3412 mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""), 3413 [], "$src1 = $_dst_" > { 3414 bits<5> src1; 3415 bits<1> src2; 3416 bits<5> src3; 3417 let accessSize = AccessSz; 3418 3419 let IClass = 0b1010; 3420 3421 let Inst{27-24} = 0b1101; 3422 let Inst{23-21} = MajOp; 3423 let Inst{20-16} = src1; 3424 let Inst{13} = src2; 3425 let Inst{12-8} = src3; 3426 let Inst{7} = 0b0; 3427 } 3428 3429def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>; 3430def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>; 3431def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>; 3432def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>; 3433 3434def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>; 3435 3436let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in 3437class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, 3438 bits<3>MajOp, bit isH = 0> 3439 : STInst <(outs), 3440 (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), 3441 mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>, 3442 AddrModeRel, ImmRegRel { 3443 bits<5> src1; 3444 bits<14> src2; // Actual address offset 3445 bits<5> src3; 3446 bits<11> offsetBits; // Represents offset encoding 3447 3448 string ImmOpStr = !cast<string>(ImmOp); 3449 3450 let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, 3451 !if (!eq(ImmOpStr, "s11_2Ext"), 13, 3452 !if (!eq(ImmOpStr, "s11_1Ext"), 12, 3453 /* s11_0Ext */ 11))); 3454 let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3}, 3455 !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2}, 3456 !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1}, 3457 /* s11_0Ext */ src2{10-0}))); 3458 let IClass = 0b1010; 3459 3460 let Inst{27} = 0b0; 3461 let Inst{26-25} = offsetBits{10-9}; 3462 let Inst{24} = 0b1; 3463 let Inst{23-21} = MajOp; 3464 let Inst{20-16} = src1; 3465 let Inst{13} = offsetBits{8}; 3466 let Inst{12-8} = src3; 3467 let Inst{7-0} = offsetBits{7-0}; 3468 } 3469 3470let opExtendable = 2, isPredicated = 1 in 3471class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, 3472 bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0> 3473 : STInst <(outs), 3474 (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), 3475 !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", 3476 ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""), 3477 [],"",V2LDST_tc_st_SLOT01 >, 3478 AddrModeRel, ImmRegRel { 3479 bits<2> src1; 3480 bits<5> src2; 3481 bits<9> src3; // Actual address offset 3482 bits<5> src4; 3483 bits<6> offsetBits; // Represents offset encoding 3484 3485 let isPredicatedNew = isPredNew; 3486 let isPredicatedFalse = PredNot; 3487 3488 string ImmOpStr = !cast<string>(ImmOp); 3489 let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, 3490 !if (!eq(ImmOpStr, "u6_2Ext"), 8, 3491 !if (!eq(ImmOpStr, "u6_1Ext"), 7, 3492 /* u6_0Ext */ 6))); 3493 let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3}, 3494 !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2}, 3495 !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1}, 3496 /* u6_0Ext */ src3{5-0}))); 3497 let IClass = 0b0100; 3498 3499 let Inst{27} = 0b0; 3500 let Inst{26} = PredNot; 3501 let Inst{25} = isPredNew; 3502 let Inst{24} = 0b0; 3503 let Inst{23-21} = MajOp; 3504 let Inst{20-16} = src2; 3505 let Inst{13} = offsetBits{5}; 3506 let Inst{12-8} = src4; 3507 let Inst{7-3} = offsetBits{4-0}; 3508 let Inst{1-0} = src1; 3509 } 3510 3511let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in 3512multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, 3513 Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> { 3514 let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { 3515 def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>; 3516 3517 // Predicated 3518 def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>; 3519 def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>; 3520 3521 // Predicated new 3522 def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp, 3523 MajOp, 0, 1, isH>; 3524 def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp, 3525 MajOp, 1, 1, isH>; 3526 } 3527} 3528 3529let addrMode = BaseImmOffset, InputType = "imm" in { 3530 let accessSize = ByteAccess in 3531 defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>; 3532 3533 let accessSize = HalfWordAccess, opExtentAlign = 1 in 3534 defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>; 3535 3536 let accessSize = WordAccess, opExtentAlign = 2 in 3537 defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>; 3538 3539 let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in 3540 defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, 3541 u6_3Ext, 0b110>; 3542 3543 let accessSize = HalfWordAccess, opExtentAlign = 1 in 3544 defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext, 3545 u6_1Ext, 0b011, 1>; 3546} 3547 3548// Patterns for generating stores, where the address takes different forms: 3549// - frameindex, 3550// - frameindex + offset, 3551// - base + offset, 3552// - simple (base address without offset). 3553// These would usually be used together (via Storex_pat defined below), but 3554// in some cases one may want to apply different properties (such as 3555// AddedComplexity) to the individual patterns. 3556class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 3557 : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; 3558class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3559 InstHexagon MI> 3560 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 3561 (MI AddrFI:$fi, imm:$Off, Value:$Rs)>; 3562class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3563 InstHexagon MI> 3564 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), 3565 (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>; 3566class Storex_simple_pat<PatFrag Store, PatFrag Value, InstHexagon MI> 3567 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), 3568 (MI IntRegs:$Rs, 0, Value:$Rt)>; 3569 3570// Patterns for generating stores, where the address takes different forms, 3571// and where the value being stored is transformed through the value modifier 3572// ValueMod. The address forms are same as above. 3573class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 3574 InstHexagon MI> 3575 : Pat<(Store Value:$Rs, AddrFI:$fi), 3576 (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; 3577class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3578 PatFrag ValueMod, InstHexagon MI> 3579 : Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)), 3580 (MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>; 3581class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, 3582 PatFrag ValueMod, InstHexagon MI> 3583 : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), 3584 (MI IntRegs:$Rs, imm:$Off, (ValueMod Value:$Rt))>; 3585class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod, 3586 InstHexagon MI> 3587 : Pat<(Store Value:$Rt, (i32 IntRegs:$Rs)), 3588 (MI IntRegs:$Rs, 0, (ValueMod Value:$Rt))>; 3589 3590multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 3591 InstHexagon MI> { 3592 def: Storex_fi_pat <Store, Value, MI>; 3593 def: Storex_fi_add_pat <Store, Value, ImmPred, MI>; 3594 def: Storex_add_pat <Store, Value, ImmPred, MI>; 3595} 3596 3597multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, 3598 PatFrag ValueMod, InstHexagon MI> { 3599 def: Storexm_fi_pat <Store, Value, ValueMod, MI>; 3600 def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>; 3601 def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>; 3602} 3603 3604// Regular stores in the DAG have two operands: value and address. 3605// Atomic stores also have two, but they are reversed: address, value. 3606// To use atomic stores with the patterns, they need to have their operands 3607// swapped. This relies on the knowledge that the F.Fragment uses names 3608// "ptr" and "val". 3609class SwapSt<PatFrag F> 3610 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>; 3611 3612let AddedComplexity = 20 in { 3613 defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>; 3614 defm: Storex_pat<truncstorei16, I32, s31_1ImmPred, S2_storerh_io>; 3615 defm: Storex_pat<store, I32, s30_2ImmPred, S2_storeri_io>; 3616 defm: Storex_pat<store, I64, s29_3ImmPred, S2_storerd_io>; 3617 3618 defm: Storex_pat<SwapSt<atomic_store_8>, I32, s32_0ImmPred, S2_storerb_io>; 3619 defm: Storex_pat<SwapSt<atomic_store_16>, I32, s31_1ImmPred, S2_storerh_io>; 3620 defm: Storex_pat<SwapSt<atomic_store_32>, I32, s30_2ImmPred, S2_storeri_io>; 3621 defm: Storex_pat<SwapSt<atomic_store_64>, I64, s29_3ImmPred, S2_storerd_io>; 3622} 3623 3624// Simple patterns should be tried with the least priority. 3625def: Storex_simple_pat<truncstorei8, I32, S2_storerb_io>; 3626def: Storex_simple_pat<truncstorei16, I32, S2_storerh_io>; 3627def: Storex_simple_pat<store, I32, S2_storeri_io>; 3628def: Storex_simple_pat<store, I64, S2_storerd_io>; 3629 3630def: Storex_simple_pat<SwapSt<atomic_store_8>, I32, S2_storerb_io>; 3631def: Storex_simple_pat<SwapSt<atomic_store_16>, I32, S2_storerh_io>; 3632def: Storex_simple_pat<SwapSt<atomic_store_32>, I32, S2_storeri_io>; 3633def: Storex_simple_pat<SwapSt<atomic_store_64>, I64, S2_storerd_io>; 3634 3635let AddedComplexity = 20 in { 3636 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>; 3637 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>; 3638 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>; 3639} 3640 3641def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 3642def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 3643def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 3644 3645// Store predicate. 3646let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, 3647 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in 3648def STriw_pred : STInst<(outs), 3649 (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1), 3650 ".error \"should not emit\"", []>; 3651 3652// S2_allocframe: Allocate stack frame. 3653let Defs = [R29, R30], Uses = [R29, R31, R30], 3654 hasSideEffects = 0, accessSize = DoubleWordAccess in 3655def S2_allocframe: ST0Inst < 3656 (outs), (ins u11_3Imm:$u11_3), 3657 "allocframe(#$u11_3)" > { 3658 bits<14> u11_3; 3659 3660 let IClass = 0b1010; 3661 let Inst{27-16} = 0b000010011101; 3662 let Inst{13-11} = 0b000; 3663 let Inst{10-0} = u11_3{13-3}; 3664 } 3665 3666// S2_storer[bhwdf]_pci: Store byte/half/word/double. 3667// S2_storer[bhwdf]_pci -> S2_storerbnew_pci 3668let Uses = [CS], isNVStorable = 1 in 3669class T_store_pci <string mnemonic, RegisterClass RC, 3670 Operand Imm, bits<4>MajOp, 3671 MemAccessSize AlignSize, string RegSrc = "Rt"> 3672 : STInst <(outs IntRegs:$_dst_), 3673 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt), 3674 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"", 3675 [] , 3676 "$Rz = $_dst_" > { 3677 bits<5> Rz; 3678 bits<7> offset; 3679 bits<1> Mu; 3680 bits<5> Rt; 3681 let accessSize = AlignSize; 3682 3683 let IClass = 0b1010; 3684 let Inst{27-25} = 0b100; 3685 let Inst{24-21} = MajOp; 3686 let Inst{20-16} = Rz; 3687 let Inst{13} = Mu; 3688 let Inst{12-8} = Rt; 3689 let Inst{7} = 0b0; 3690 let Inst{6-3} = 3691 !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3}, 3692 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, 3693 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, 3694 /* ByteAccess */ offset{3-0}))); 3695 let Inst{1} = 0b0; 3696 } 3697 3698def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000, 3699 ByteAccess>; 3700def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010, 3701 HalfWordAccess>; 3702def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011, 3703 HalfWordAccess, "Rt.h">; 3704def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100, 3705 WordAccess>; 3706def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110, 3707 DoubleWordAccess>; 3708 3709let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in 3710class T_storenew_pci <string mnemonic, Operand Imm, 3711 bits<2>MajOp, MemAccessSize AlignSize> 3712 : NVInst < (outs IntRegs:$_dst_), 3713 (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt), 3714 #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new", 3715 [], 3716 "$Rz = $_dst_"> { 3717 bits<5> Rz; 3718 bits<6> offset; 3719 bits<1> Mu; 3720 bits<3> Nt; 3721 3722 let accessSize = AlignSize; 3723 3724 let IClass = 0b1010; 3725 let Inst{27-21} = 0b1001101; 3726 let Inst{20-16} = Rz; 3727 let Inst{13} = Mu; 3728 let Inst{12-11} = MajOp; 3729 let Inst{10-8} = Nt; 3730 let Inst{7} = 0b0; 3731 let Inst{6-3} = 3732 !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, 3733 !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, 3734 /* ByteAccess */ offset{3-0})); 3735 let Inst{1} = 0b0; 3736 } 3737 3738def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>; 3739def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>; 3740def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>; 3741 3742//===----------------------------------------------------------------------===// 3743// Circular stores - Pseudo 3744// 3745// Please note that the input operand order in the pseudo instructions 3746// doesn't match with the real instructions. Pseudo instructions operand 3747// order should mimics the ordering in the intrinsics. 3748//===----------------------------------------------------------------------===// 3749let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in 3750class T_store_pci_pseudo <string opc, RegisterClass RC> 3751 : STInstPI<(outs IntRegs:$_dst_), 3752 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3, s4Imm:$src4), 3753 ".error \""#opc#"($src1++#$src4:circ($src3)) = $src2\"", 3754 [], "$_dst_ = $src1">; 3755 3756def S2_storerb_pci_pseudo : T_store_pci_pseudo <"memb", IntRegs>; 3757def S2_storerh_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>; 3758def S2_storerf_pci_pseudo : T_store_pci_pseudo <"memh", IntRegs>; 3759def S2_storeri_pci_pseudo : T_store_pci_pseudo <"memw", IntRegs>; 3760def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>; 3761 3762//===----------------------------------------------------------------------===// 3763// Circular stores with auto-increment register 3764//===----------------------------------------------------------------------===// 3765let Uses = [CS], isNVStorable = 1 in 3766class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, 3767 MemAccessSize AlignSize, string RegSrc = "Rt"> 3768 : STInst <(outs IntRegs:$_dst_), 3769 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt), 3770 #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"", 3771 [], 3772 "$Rz = $_dst_" > { 3773 bits<5> Rz; 3774 bits<1> Mu; 3775 bits<5> Rt; 3776 3777 let accessSize = AlignSize; 3778 3779 let IClass = 0b1010; 3780 let Inst{27-25} = 0b100; 3781 let Inst{24-21} = MajOp; 3782 let Inst{20-16} = Rz; 3783 let Inst{13} = Mu; 3784 let Inst{12-8} = Rt; 3785 let Inst{7} = 0b0; 3786 let Inst{1} = 0b1; 3787 } 3788 3789def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>; 3790def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>; 3791def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>; 3792def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>; 3793def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011, 3794 HalfWordAccess, "Rt.h">; 3795 3796//===----------------------------------------------------------------------===// 3797// Circular .new stores with auto-increment register 3798//===----------------------------------------------------------------------===// 3799let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in 3800class T_storenew_pcr <string mnemonic, bits<2>MajOp, 3801 MemAccessSize AlignSize> 3802 : NVInst <(outs IntRegs:$_dst_), 3803 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), 3804 #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" , 3805 [] , 3806 "$Rz = $_dst_"> { 3807 bits<5> Rz; 3808 bits<1> Mu; 3809 bits<3> Nt; 3810 3811 let accessSize = AlignSize; 3812 3813 let IClass = 0b1010; 3814 let Inst{27-21} = 0b1001101; 3815 let Inst{20-16} = Rz; 3816 let Inst{13} = Mu; 3817 let Inst{12-11} = MajOp; 3818 let Inst{10-8} = Nt; 3819 let Inst{7} = 0b0; 3820 let Inst{1} = 0b1; 3821 } 3822 3823def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>; 3824def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>; 3825def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>; 3826 3827//===----------------------------------------------------------------------===// 3828// Bit-reversed stores with auto-increment register 3829//===----------------------------------------------------------------------===// 3830let hasSideEffects = 0 in 3831class T_store_pbr<string mnemonic, RegisterClass RC, 3832 MemAccessSize addrSize, bits<3> majOp, 3833 bit isHalf = 0> 3834 : STInst 3835 <(outs IntRegs:$_dst_), 3836 (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src), 3837 #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""), 3838 [], "$Rz = $_dst_" > { 3839 3840 let accessSize = addrSize; 3841 3842 bits<5> Rz; 3843 bits<1> Mu; 3844 bits<5> src; 3845 3846 let IClass = 0b1010; 3847 3848 let Inst{27-24} = 0b1111; 3849 let Inst{23-21} = majOp; 3850 let Inst{7} = 0b0; 3851 let Inst{20-16} = Rz; 3852 let Inst{13} = Mu; 3853 let Inst{12-8} = src; 3854 } 3855 3856let isNVStorable = 1 in { 3857 let BaseOpcode = "S2_storerb_pbr" in 3858 def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess, 3859 0b000>, NewValueRel; 3860 let BaseOpcode = "S2_storerh_pbr" in 3861 def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 3862 0b010>, NewValueRel; 3863 let BaseOpcode = "S2_storeri_pbr" in 3864 def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess, 3865 0b100>, NewValueRel; 3866} 3867 3868def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>; 3869def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>; 3870 3871//===----------------------------------------------------------------------===// 3872// Bit-reversed .new stores with auto-increment register 3873//===----------------------------------------------------------------------===// 3874let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, 3875 hasSideEffects = 0 in 3876class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp> 3877 : NVInst <(outs IntRegs:$_dst_), 3878 (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), 3879 #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [], 3880 "$Rz = $_dst_">, NewValueRel { 3881 let accessSize = addrSize; 3882 bits<5> Rz; 3883 bits<1> Mu; 3884 bits<3> Nt; 3885 3886 let IClass = 0b1010; 3887 3888 let Inst{27-21} = 0b1111101; 3889 let Inst{12-11} = majOp; 3890 let Inst{7} = 0b0; 3891 let Inst{20-16} = Rz; 3892 let Inst{13} = Mu; 3893 let Inst{10-8} = Nt; 3894 } 3895 3896let BaseOpcode = "S2_storerb_pbr" in 3897def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>; 3898 3899let BaseOpcode = "S2_storerh_pbr" in 3900def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>; 3901 3902let BaseOpcode = "S2_storeri_pbr" in 3903def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>; 3904 3905//===----------------------------------------------------------------------===// 3906// Bit-reversed stores - Pseudo 3907// 3908// Please note that the input operand order in the pseudo instructions 3909// doesn't match with the real instructions. Pseudo instructions operand 3910// order should mimics the ordering in the intrinsics. 3911//===----------------------------------------------------------------------===// 3912let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in 3913class T_store_pbr_pseudo <string opc, RegisterClass RC> 3914 : STInstPI<(outs IntRegs:$_dst_), 3915 (ins IntRegs:$src1, RC:$src2, IntRegs:$src3), 3916 ".error \""#opc#"($src1++$src3:brev) = $src2\"", 3917 [], "$_dst_ = $src1">; 3918 3919def S2_storerb_pbr_pseudo : T_store_pbr_pseudo <"memb", IntRegs>; 3920def S2_storerh_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>; 3921def S2_storeri_pbr_pseudo : T_store_pbr_pseudo <"memw", IntRegs>; 3922def S2_storerf_pbr_pseudo : T_store_pbr_pseudo <"memh", IntRegs>; 3923def S2_storerd_pbr_pseudo : T_store_pbr_pseudo <"memd", DoubleRegs>; 3924 3925//===----------------------------------------------------------------------===// 3926// ST - 3927//===----------------------------------------------------------------------===// 3928 3929//===----------------------------------------------------------------------===// 3930// Template class for S_2op instructions. 3931//===----------------------------------------------------------------------===// 3932let hasSideEffects = 0 in 3933class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, 3934 RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> 3935 : SInst <(outs RCOut:$dst), (ins RCIn:$src), 3936 "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""), 3937 [], "", S_2op_tc_1_SLOT23 > { 3938 bits<5> dst; 3939 bits<5> src; 3940 3941 let IClass = 0b1000; 3942 3943 let Inst{27-24} = RegTyBits; 3944 let Inst{23-22} = MajOp; 3945 let Inst{21} = 0b0; 3946 let Inst{20-16} = src; 3947 let Inst{7-5} = MinOp; 3948 let Inst{4-0} = dst; 3949 } 3950 3951class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp> 3952 : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>; 3953 3954let hasNewValue = 1 in 3955class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> 3956 : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>; 3957 3958let hasNewValue = 1 in 3959class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> 3960 : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>; 3961 3962// Vector sign/zero extend 3963let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 3964 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>; 3965 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>; 3966 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>; 3967 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>; 3968} 3969 3970// Vector splat bytes/halfwords 3971let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 3972 def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>; 3973 def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>; 3974} 3975 3976// Sign extend word to doubleword 3977def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; 3978 3979def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; 3980 3981// Vector saturate and pack 3982let Defs = [USR_OVF] in { 3983 def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>; 3984 def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>; 3985 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>; 3986 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>; 3987 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>; 3988 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>; 3989} 3990 3991// Vector truncate 3992def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>; 3993def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>; 3994 3995// Swizzle the bytes of a word 3996def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; 3997 3998// Saturate 3999let Defs = [USR_OVF] in { 4000 def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>; 4001 def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>; 4002 def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; 4003 def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; 4004 def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; 4005 def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>; 4006} 4007 4008let Itinerary = S_2op_tc_2_SLOT23 in { 4009 // Vector round and pack 4010 def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>; 4011 4012 let Defs = [USR_OVF] in 4013 def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>; 4014 4015 // Bit reverse 4016 def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>; 4017 4018 // Absolute value word 4019 def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>; 4020 4021 let Defs = [USR_OVF] in 4022 def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>; 4023 4024 // Negate with saturation 4025 let Defs = [USR_OVF] in 4026 def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>; 4027} 4028 4029def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)), 4030 (i32 (sub 0, (i32 IntRegs:$src))), 4031 (i32 IntRegs:$src))), 4032 (A2_abs IntRegs:$src)>; 4033 4034let AddedComplexity = 50 in 4035def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)), 4036 (i32 IntRegs:$src)), 4037 (sra (i32 IntRegs:$src), (i32 31)))), 4038 (A2_abs IntRegs:$src)>; 4039 4040class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, 4041 RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp, 4042 bit isSat, bit isRnd, list<dag> pattern = []> 4043 : SInst <(outs RCOut:$dst), 4044 (ins RCIn:$src, u5Imm:$u5), 4045 "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "") 4046 #!if(isRnd, ":rnd", ""), 4047 pattern, "", S_2op_tc_2_SLOT23> { 4048 bits<5> dst; 4049 bits<5> src; 4050 bits<5> u5; 4051 4052 let IClass = 0b1000; 4053 4054 let Inst{27-24} = RegTyBits; 4055 let Inst{23-21} = MajOp; 4056 let Inst{20-16} = src; 4057 let Inst{13} = 0b0; 4058 let Inst{12-8} = u5; 4059 let Inst{7-5} = MinOp; 4060 let Inst{4-0} = dst; 4061 } 4062 4063class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp> 4064 : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>; 4065 4066let hasNewValue = 1 in 4067class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp> 4068 : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>; 4069 4070let hasNewValue = 1 in 4071class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp, 4072 bit isSat = 0, bit isRnd = 0, list<dag> pattern = []> 4073 : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, 4074 isSat, isRnd, pattern>; 4075 4076class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd> 4077 : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0, 4078 [(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src), 4079 (u5ImmPred:$u5)))]>; 4080 4081// Vector arithmetic shift right by immediate with truncate and pack 4082def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>; 4083 4084// Arithmetic/logical shift right/left by immediate 4085let Itinerary = S_2op_tc_1_SLOT23 in { 4086 def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>; 4087 def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>; 4088 def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>; 4089} 4090 4091// Shift left by immediate with saturation 4092let Defs = [USR_OVF] in 4093def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>; 4094 4095// Shift right with round 4096def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>; 4097 4098let isAsmParserOnly = 1 in 4099def S2_asr_i_r_rnd_goodsyntax 4100 : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5), 4101 "$dst = asrrnd($src, #$u5)", 4102 [], "", S_2op_tc_1_SLOT23>; 4103 4104let isAsmParserOnly = 1 in 4105def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src), 4106 "$dst = not($src)">; 4107 4108def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)), 4109 (i32 1))), 4110 (i32 1))), 4111 (S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>; 4112 4113class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0> 4114 : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), 4115 "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> { 4116 bits<5> Rss; 4117 bits<5> Rdd; 4118 let IClass = 0b1000; 4119 let Inst{27-24} = 0; 4120 let Inst{23-22} = MajOp; 4121 let Inst{20-16} = Rss; 4122 let Inst{7-5} = minOp; 4123 let Inst{4-0} = Rdd; 4124} 4125 4126def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>; 4127def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>; 4128def A2_notp : T_S2op_3 <"not", 0b10, 0b100>; 4129 4130// Innterleave/deinterleave 4131def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>; 4132def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; 4133 4134// Vector Complex conjugate 4135def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; 4136 4137// Vector saturate without pack 4138def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>; 4139def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>; 4140def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>; 4141def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>; 4142 4143// Vector absolute value halfwords with and without saturation 4144// Rdd64=vabsh(Rss64)[:sat] 4145def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>; 4146def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>; 4147 4148// Vector absolute value words with and without saturation 4149def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>; 4150def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>; 4151 4152def : Pat<(not (i64 DoubleRegs:$src1)), 4153 (A2_notp DoubleRegs:$src1)>; 4154 4155//===----------------------------------------------------------------------===// 4156// STYPE/BIT + 4157//===----------------------------------------------------------------------===// 4158// Bit count 4159 4160let hasSideEffects = 0, hasNewValue = 1 in 4161class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32, 4162 dag Out, dag Inp> 4163 : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> { 4164 bits<5> Rs; 4165 bits<5> Rd; 4166 let IClass = 0b1000; 4167 let Inst{27} = 0b1; 4168 let Inst{26} = Is32; 4169 let Inst{25-24} = 0b00; 4170 let Inst{23-21} = MajOp; 4171 let Inst{20-16} = Rs; 4172 let Inst{7-5} = MinOp; 4173 let Inst{4-0} = Rd; 4174} 4175 4176class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp> 4177 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1, 4178 (outs IntRegs:$Rd), (ins IntRegs:$Rs)>; 4179 4180class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp> 4181 : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0, 4182 (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>; 4183 4184def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>; 4185def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>; 4186def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>; 4187def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>; 4188def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>; 4189def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>; 4190def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>; 4191def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>; 4192def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>; 4193 4194def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>; 4195def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>; 4196def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>; 4197def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>; 4198def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>; 4199def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>; 4200 4201// Bit set/clear/toggle 4202 4203let hasSideEffects = 0, hasNewValue = 1 in 4204class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp> 4205 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5), 4206 "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> { 4207 bits<5> Rd; 4208 bits<5> Rs; 4209 bits<5> u5; 4210 let IClass = 0b1000; 4211 let Inst{27-21} = 0b1100110; 4212 let Inst{20-16} = Rs; 4213 let Inst{13} = 0b0; 4214 let Inst{12-8} = u5; 4215 let Inst{7-5} = MinOp; 4216 let Inst{4-0} = Rd; 4217} 4218 4219let hasSideEffects = 0, hasNewValue = 1 in 4220class T_SCT_BIT_REG<string MnOp, bits<2> MinOp> 4221 : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), 4222 "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> { 4223 bits<5> Rd; 4224 bits<5> Rs; 4225 bits<5> Rt; 4226 let IClass = 0b1100; 4227 let Inst{27-22} = 0b011010; 4228 let Inst{20-16} = Rs; 4229 let Inst{12-8} = Rt; 4230 let Inst{7-6} = MinOp; 4231 let Inst{4-0} = Rd; 4232} 4233 4234def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>; 4235def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>; 4236def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>; 4237def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>; 4238def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>; 4239def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>; 4240 4241def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))), 4242 (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4243def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))), 4244 (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4245def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))), 4246 (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4247def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))), 4248 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4249def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), 4250 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4251def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))), 4252 (S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>; 4253 4254// Bit test 4255 4256let hasSideEffects = 0 in 4257class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp> 4258 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5), 4259 "$Pd = "#MnOp#"($Rs, #$u5)", 4260 [], "", S_2op_tc_2early_SLOT23> { 4261 bits<2> Pd; 4262 bits<5> Rs; 4263 bits<5> u5; 4264 let IClass = 0b1000; 4265 let Inst{27-24} = 0b0101; 4266 let Inst{23-21} = MajOp; 4267 let Inst{20-16} = Rs; 4268 let Inst{13} = 0; 4269 let Inst{12-8} = u5; 4270 let Inst{1-0} = Pd; 4271} 4272 4273let hasSideEffects = 0 in 4274class T_TEST_BIT_REG<string MnOp, bit IsNeg> 4275 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 4276 "$Pd = "#MnOp#"($Rs, $Rt)", 4277 [], "", S_3op_tc_2early_SLOT23> { 4278 bits<2> Pd; 4279 bits<5> Rs; 4280 bits<5> Rt; 4281 let IClass = 0b1100; 4282 let Inst{27-22} = 0b011100; 4283 let Inst{21} = IsNeg; 4284 let Inst{20-16} = Rs; 4285 let Inst{12-8} = Rt; 4286 let Inst{1-0} = Pd; 4287} 4288 4289def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>; 4290def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>; 4291 4292let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 4293 def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)), 4294 (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>; 4295 def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)), 4296 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>; 4297 def: Pat<(i1 (trunc (i32 IntRegs:$Rs))), 4298 (S2_tstbit_i IntRegs:$Rs, 0)>; 4299 def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))), 4300 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 4301} 4302 4303let hasSideEffects = 0 in 4304class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg> 4305 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6), 4306 "$Pd = "#MnOp#"($Rs, #$u6)", 4307 [], "", S_2op_tc_2early_SLOT23> { 4308 bits<2> Pd; 4309 bits<5> Rs; 4310 bits<6> u6; 4311 let IClass = 0b1000; 4312 let Inst{27-24} = 0b0101; 4313 let Inst{23-22} = MajOp; 4314 let Inst{21} = IsNeg; 4315 let Inst{20-16} = Rs; 4316 let Inst{13-8} = u6; 4317 let Inst{1-0} = Pd; 4318} 4319 4320let hasSideEffects = 0 in 4321class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg> 4322 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), 4323 "$Pd = "#MnOp#"($Rs, $Rt)", 4324 [], "", S_3op_tc_2early_SLOT23> { 4325 bits<2> Pd; 4326 bits<5> Rs; 4327 bits<5> Rt; 4328 let IClass = 0b1100; 4329 let Inst{27-24} = 0b0111; 4330 let Inst{23-22} = MajOp; 4331 let Inst{21} = IsNeg; 4332 let Inst{20-16} = Rs; 4333 let Inst{12-8} = Rt; 4334 let Inst{1-0} = Pd; 4335} 4336 4337def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>; 4338def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>; 4339def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>; 4340 4341let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 4342 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)), 4343 (C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>; 4344 def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)), 4345 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>; 4346} 4347 4348let AddedComplexity = 10 in // Complexity greater than compare reg-reg. 4349def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)), 4350 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>; 4351 4352//===----------------------------------------------------------------------===// 4353// STYPE/BIT - 4354//===----------------------------------------------------------------------===// 4355 4356//===----------------------------------------------------------------------===// 4357// STYPE/COMPLEX + 4358//===----------------------------------------------------------------------===// 4359//===----------------------------------------------------------------------===// 4360// STYPE/COMPLEX - 4361//===----------------------------------------------------------------------===// 4362 4363//===----------------------------------------------------------------------===// 4364// XTYPE/PERM + 4365//===----------------------------------------------------------------------===// 4366 4367def: Pat<(or (or (shl (or (shl (i32 (extloadi8 (add (i32 IntRegs:$b), 3))), 4368 (i32 8)), 4369 (i32 (zextloadi8 (add (i32 IntRegs:$b), 2)))), 4370 (i32 16)), 4371 (shl (i32 (zextloadi8 (add (i32 IntRegs:$b), 1))), (i32 8))), 4372 (zextloadi8 (i32 IntRegs:$b))), 4373 (A2_swiz (L2_loadri_io IntRegs:$b, 0))>; 4374 4375//===----------------------------------------------------------------------===// 4376// XTYPE/PERM - 4377//===----------------------------------------------------------------------===// 4378 4379//===----------------------------------------------------------------------===// 4380// STYPE/PRED + 4381//===----------------------------------------------------------------------===// 4382 4383// Predicate transfer. 4384let hasSideEffects = 0, hasNewValue = 1 in 4385def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps), 4386 "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> { 4387 bits<5> Rd; 4388 bits<2> Ps; 4389 4390 let IClass = 0b1000; 4391 let Inst{27-24} = 0b1001; 4392 let Inst{22} = 0b1; 4393 let Inst{17-16} = Ps; 4394 let Inst{4-0} = Rd; 4395} 4396 4397// Transfer general register to predicate. 4398let hasSideEffects = 0 in 4399def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs), 4400 "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> { 4401 bits<2> Pd; 4402 bits<5> Rs; 4403 4404 let IClass = 0b1000; 4405 let Inst{27-21} = 0b0101010; 4406 let Inst{20-16} = Rs; 4407 let Inst{1-0} = Pd; 4408} 4409 4410let hasSideEffects = 0, isCodeGenOnly = 1 in 4411def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src), 4412 "$dst = $src">; 4413 4414 4415// Patterns for loads of i1: 4416def: Pat<(i1 (load AddrFI:$fi)), 4417 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>; 4418def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))), 4419 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>; 4420def: Pat<(i1 (load (i32 IntRegs:$Rs))), 4421 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>; 4422 4423def I1toI32: OutPatFrag<(ops node:$Rs), 4424 (C2_muxii (i1 $Rs), 1, 0)>; 4425 4426def I32toI1: OutPatFrag<(ops node:$Rs), 4427 (i1 (C2_tfrrp (i32 $Rs)))>; 4428 4429defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>; 4430def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>; 4431 4432//===----------------------------------------------------------------------===// 4433// STYPE/PRED - 4434//===----------------------------------------------------------------------===// 4435 4436//===----------------------------------------------------------------------===// 4437// STYPE/SHIFT + 4438//===----------------------------------------------------------------------===// 4439class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp, 4440 Operand Imm, list<dag> pattern = [], bit isRnd = 0> 4441 : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2), 4442 "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""), 4443 pattern> { 4444 bits<5> src1; 4445 bits<5> dst; 4446 let IClass = 0b1000; 4447 let Inst{27-24} = 0; 4448 let Inst{23-21} = MajOp; 4449 let Inst{20-16} = src1; 4450 let Inst{7-5} = MinOp; 4451 let Inst{4-0} = dst; 4452} 4453 4454class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp> 4455 : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm, 4456 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1), 4457 u6ImmPred:$src2))]> { 4458 bits<6> src2; 4459 let Inst{13-8} = src2; 4460} 4461 4462// Shift by immediate. 4463def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>; 4464def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>; 4465def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>; 4466 4467// Shift left by small amount and add. 4468let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in 4469def S2_addasl_rrri: SInst <(outs IntRegs:$Rd), 4470 (ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3), 4471 "$Rd = addasl($Rt, $Rs, #$u3)" , 4472 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt), 4473 (shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))], 4474 "", S_3op_tc_2_SLOT23> { 4475 bits<5> Rd; 4476 bits<5> Rt; 4477 bits<5> Rs; 4478 bits<3> u3; 4479 4480 let IClass = 0b1100; 4481 4482 let Inst{27-21} = 0b0100000; 4483 let Inst{20-16} = Rs; 4484 let Inst{13} = 0b0; 4485 let Inst{12-8} = Rt; 4486 let Inst{7-5} = u3; 4487 let Inst{4-0} = Rd; 4488 } 4489 4490//===----------------------------------------------------------------------===// 4491// STYPE/SHIFT - 4492//===----------------------------------------------------------------------===// 4493 4494//===----------------------------------------------------------------------===// 4495// STYPE/VH + 4496//===----------------------------------------------------------------------===// 4497//===----------------------------------------------------------------------===// 4498// STYPE/VH - 4499//===----------------------------------------------------------------------===// 4500 4501//===----------------------------------------------------------------------===// 4502// STYPE/VW + 4503//===----------------------------------------------------------------------===// 4504//===----------------------------------------------------------------------===// 4505// STYPE/VW - 4506//===----------------------------------------------------------------------===// 4507 4508//===----------------------------------------------------------------------===// 4509// SYSTEM/SUPER + 4510//===----------------------------------------------------------------------===// 4511 4512//===----------------------------------------------------------------------===// 4513// SYSTEM/USER + 4514//===----------------------------------------------------------------------===// 4515def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; 4516 4517let hasSideEffects = 1, isSoloAX = 1 in 4518def Y2_barrier : SYSInst<(outs), (ins), 4519 "barrier", 4520 [(HexagonBARRIER)],"",ST_tc_st_SLOT0> { 4521 let Inst{31-28} = 0b1010; 4522 let Inst{27-21} = 0b1000000; 4523} 4524 4525//===----------------------------------------------------------------------===// 4526// SYSTEM/SUPER - 4527//===----------------------------------------------------------------------===// 4528 4529// Generate frameindex addresses. 4530let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, 4531 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in 4532def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$fi, s32Imm:$Off), "">; 4533 4534//===----------------------------------------------------------------------===// 4535// CRUSER - Type. 4536//===----------------------------------------------------------------------===// 4537// HW loop 4538let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, 4539 opExtendable = 0, hasSideEffects = 0 in 4540class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> 4541 : CRInst<(outs), (ins brOp:$offset, u10Imm:$src2), 4542 #mnemonic#"($offset, #$src2)", 4543 [], "" , CR_tc_3x_SLOT3> { 4544 bits<9> offset; 4545 bits<10> src2; 4546 4547 let IClass = 0b0110; 4548 4549 let Inst{27-22} = 0b100100; 4550 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); 4551 let Inst{20-16} = src2{9-5}; 4552 let Inst{12-8} = offset{8-4}; 4553 let Inst{7-5} = src2{4-2}; 4554 let Inst{4-3} = offset{3-2}; 4555 let Inst{1-0} = src2{1-0}; 4556} 4557 4558let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, 4559 opExtendable = 0, hasSideEffects = 0 in 4560class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> 4561 : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), 4562 #mnemonic#"($offset, $src2)", 4563 [], "" ,CR_tc_3x_SLOT3> { 4564 bits<9> offset; 4565 bits<5> src2; 4566 4567 let IClass = 0b0110; 4568 4569 let Inst{27-22} = 0b000000; 4570 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); 4571 let Inst{20-16} = src2; 4572 let Inst{12-8} = offset{8-4}; 4573 let Inst{4-3} = offset{3-2}; 4574 } 4575 4576multiclass LOOP_ri<string mnemonic> { 4577 def i : LOOP_iBase<mnemonic, brtarget>; 4578 def r : LOOP_rBase<mnemonic, brtarget>; 4579 4580 let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { 4581 def iext: LOOP_iBase<mnemonic, brtargetExt, 1>; 4582 def rext: LOOP_rBase<mnemonic, brtargetExt, 1>; 4583 } 4584} 4585 4586 4587let Defs = [SA0, LC0, USR] in 4588defm J2_loop0 : LOOP_ri<"loop0">; 4589 4590// Interestingly only loop0's appear to set usr.lpcfg 4591let Defs = [SA1, LC1] in 4592defm J2_loop1 : LOOP_ri<"loop1">; 4593 4594let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 4595 Defs = [PC, LC0], Uses = [SA0, LC0] in { 4596def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset), 4597 ":endloop0", 4598 []>; 4599} 4600 4601let isBranch = 1, isTerminator = 1, hasSideEffects = 0, 4602 Defs = [PC, LC1], Uses = [SA1, LC1] in { 4603def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset), 4604 ":endloop1", 4605 []>; 4606} 4607 4608// Pipelined loop instructions, sp[123]loop0 4609let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, 4610 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, 4611 opExtendable = 0, isPredicateLate = 1 in 4612class SPLOOP_iBase<string SP, bits<2> op> 4613 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10), 4614 "p3 = sp"#SP#"loop0($r7_2, #$U10)" > { 4615 bits<9> r7_2; 4616 bits<10> U10; 4617 4618 let IClass = 0b0110; 4619 4620 let Inst{22-21} = op; 4621 let Inst{27-23} = 0b10011; 4622 let Inst{20-16} = U10{9-5}; 4623 let Inst{12-8} = r7_2{8-4}; 4624 let Inst{7-5} = U10{4-2}; 4625 let Inst{4-3} = r7_2{3-2}; 4626 let Inst{1-0} = U10{1-0}; 4627 } 4628 4629let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, 4630 isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, 4631 opExtendable = 0, isPredicateLate = 1 in 4632class SPLOOP_rBase<string SP, bits<2> op> 4633 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs), 4634 "p3 = sp"#SP#"loop0($r7_2, $Rs)" > { 4635 bits<9> r7_2; 4636 bits<5> Rs; 4637 4638 let IClass = 0b0110; 4639 4640 let Inst{22-21} = op; 4641 let Inst{27-23} = 0b00001; 4642 let Inst{20-16} = Rs; 4643 let Inst{12-8} = r7_2{8-4}; 4644 let Inst{4-3} = r7_2{3-2}; 4645 } 4646 4647multiclass SPLOOP_ri<string mnemonic, bits<2> op> { 4648 def i : SPLOOP_iBase<mnemonic, op>; 4649 def r : SPLOOP_rBase<mnemonic, op>; 4650} 4651 4652defm J2_ploop1s : SPLOOP_ri<"1", 0b01>; 4653defm J2_ploop2s : SPLOOP_ri<"2", 0b10>; 4654defm J2_ploop3s : SPLOOP_ri<"3", 0b11>; 4655 4656// if (Rs[!>=<]=#0) jump:[t/nt] 4657let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0, 4658 hasSideEffects = 0 in 4659class J2_jump_0_Base<string compare, bit isTak, bits<2> op> 4660 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2), 4661 "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > { 4662 bits<5> Rs; 4663 bits<15> r13_2; 4664 4665 let IClass = 0b0110; 4666 4667 let Inst{27-24} = 0b0001; 4668 let Inst{23-22} = op; 4669 let Inst{12} = isTak; 4670 let Inst{21} = r13_2{14}; 4671 let Inst{20-16} = Rs; 4672 let Inst{11-1} = r13_2{12-2}; 4673 let Inst{13} = r13_2{13}; 4674 } 4675 4676multiclass J2_jump_compare_0<string compare, bits<2> op> { 4677 def NAME : J2_jump_0_Base<compare, 0, op>; 4678 def NAME#pt : J2_jump_0_Base<compare, 1, op>; 4679} 4680 4681defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>; 4682defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>; 4683defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>; 4684defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>; 4685 4686// Transfer to/from Control/GPR Guest/GPR 4687let hasSideEffects = 0 in 4688class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble> 4689 : CRInst <(outs CTRC:$dst), (ins RC:$src), 4690 "$dst = $src", [], "", CR_tc_3x_SLOT3> { 4691 bits<5> dst; 4692 bits<5> src; 4693 4694 let IClass = 0b0110; 4695 4696 let Inst{27-25} = 0b001; 4697 let Inst{24} = isDouble; 4698 let Inst{23-21} = 0b001; 4699 let Inst{20-16} = src; 4700 let Inst{4-0} = dst; 4701 } 4702 4703def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>; 4704def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>; 4705def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; 4706def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; 4707 4708let hasSideEffects = 0 in 4709class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle> 4710 : CRInst <(outs RC:$dst), (ins CTRC:$src), 4711 "$dst = $src", [], "", CR_tc_3x_SLOT3> { 4712 bits<5> dst; 4713 bits<5> src; 4714 4715 let IClass = 0b0110; 4716 4717 let Inst{27-26} = 0b10; 4718 let Inst{25} = isSingle; 4719 let Inst{24-21} = 0b0000; 4720 let Inst{20-16} = src; 4721 let Inst{4-0} = dst; 4722 } 4723 4724let hasNewValue = 1, opNewValue = 0 in 4725def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>; 4726def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>; 4727def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; 4728def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; 4729 4730// Y4_trace: Send value to etm trace. 4731let isSoloAX = 1, hasSideEffects = 0 in 4732def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs), 4733 "trace($Rs)"> { 4734 bits<5> Rs; 4735 4736 let IClass = 0b0110; 4737 let Inst{27-21} = 0b0010010; 4738 let Inst{20-16} = Rs; 4739 } 4740 4741// Support for generating global address. 4742// Taken from X86InstrInfo.td. 4743def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 4744 SDTCisVT<1, i32>, 4745 SDTCisPtrTy<0>]>; 4746def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; 4747def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; 4748 4749// HI/LO Instructions 4750let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, 4751 hasNewValue = 1, opNewValue = 0 in 4752class REG_IMMED<string RegHalf, string Op, bit Rs, bits<3> MajOp, bit MinOp> 4753 : ALU32_ri<(outs IntRegs:$dst), 4754 (ins i32imm:$imm_value), 4755 "$dst"#RegHalf#" = #"#Op#"($imm_value)", []> { 4756 bits<5> dst; 4757 bits<32> imm_value; 4758 let IClass = 0b0111; 4759 4760 let Inst{27} = Rs; 4761 let Inst{26-24} = MajOp; 4762 let Inst{21} = MinOp; 4763 let Inst{20-16} = dst; 4764 let Inst{23-22} = !if (!eq(Op, "LO"), imm_value{15-14}, imm_value{31-30}); 4765 let Inst{13-0} = !if (!eq(Op, "LO"), imm_value{13-0}, imm_value{29-16}); 4766} 4767 4768let isAsmParserOnly = 1 in { 4769 def LO : REG_IMMED<".l", "LO", 0b0, 0b001, 0b1>; 4770 def LO_H : REG_IMMED<".l", "HI", 0b0, 0b001, 0b1>; 4771 def HI : REG_IMMED<".h", "HI", 0b0, 0b010, 0b1>; 4772 def HI_L : REG_IMMED<".h", "LO", 0b0, 0b010, 0b1>; 4773} 4774 4775let isMoveImm = 1, isCodeGenOnly = 1 in 4776def LO_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), 4777 "$dst.l = #LO($label@GOTREL)", 4778 []>; 4779 4780let isMoveImm = 1, isCodeGenOnly = 1 in 4781def HI_PIC : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), 4782 "$dst.h = #HI($label@GOTREL)", 4783 []>; 4784 4785let isReMaterializable = 1, isMoveImm = 1, 4786 isCodeGenOnly = 1, hasSideEffects = 0 in 4787def HI_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4788 "$dst.h = #HI($global@GOT)", 4789 []>; 4790 4791let isReMaterializable = 1, isMoveImm = 1, 4792 isCodeGenOnly = 1, hasSideEffects = 0 in 4793def LO_GOT : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4794 "$dst.l = #LO($global@GOT)", 4795 []>; 4796 4797let isReMaterializable = 1, isMoveImm = 1, 4798 isCodeGenOnly = 1, hasSideEffects = 0 in 4799def HI_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4800 "$dst.h = #HI($global@GOTREL)", 4801 []>; 4802 4803let isReMaterializable = 1, isMoveImm = 1, 4804 isCodeGenOnly = 1, hasSideEffects = 0 in 4805def LO_GOTREL : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), 4806 "$dst.l = #LO($global@GOTREL)", 4807 []>; 4808 4809// This pattern is incorrect. When we add small data, we should change 4810// this pattern to use memw(#foo). 4811// This is for sdata. 4812let isMoveImm = 1, isAsmParserOnly = 1 in 4813def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global), 4814 "$dst = CONST32(#$global)", 4815 [(set (i32 IntRegs:$dst), 4816 (load (HexagonCONST32 tglobaltlsaddr:$global)))]>; 4817 4818let isReMaterializable = 1, isMoveImm = 1 in 4819def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt), 4820 "$dst = CONST32(#$jt)", 4821 [(set (i32 IntRegs:$dst), 4822 (HexagonCONST32 tjumptable:$jt))]>; 4823 4824let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in 4825def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global), 4826 "$dst = CONST32(#$global)", 4827 [(set (i32 IntRegs:$dst), imm:$global) ]>; 4828 4829// Map TLS addressses to a CONST32 instruction 4830def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>; 4831def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>; 4832 4833let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in 4834def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label), 4835 "$dst = CONST32($label)", 4836 [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>; 4837 4838let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in 4839def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global), 4840 "$dst = CONST64(#$global)", 4841 [(set (i64 DoubleRegs:$dst), imm:$global)]>; 4842 4843let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 4844 isCodeGenOnly = 1 in 4845def TFR_PdTrue : SInst<(outs PredRegs:$dst), (ins), "", 4846 [(set (i1 PredRegs:$dst), 1)]>; 4847 4848let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 4849 isCodeGenOnly = 1 in 4850def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins), "$dst = xor($dst, $dst)", 4851 [(set (i1 PredRegs:$dst), 0)]>; 4852 4853// Pseudo instructions. 4854def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 4855def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 4856 SDTCisVT<1, i32> ]>; 4857 4858def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 4859 [SDNPHasChain, SDNPOutGlue]>; 4860def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 4861 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 4862 4863def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 4864 4865// For tailcalls a HexagonTCRet SDNode has 3 SDNode Properties - a chain, 4866// Optional Flag and Variable Arguments. 4867// Its 1 Operand has pointer type. 4868def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall, 4869 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 4870 4871let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in 4872def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 4873 ".error \"should not emit\" ", 4874 [(callseq_start timm:$amt)]>; 4875 4876let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in 4877def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 4878 ".error \"should not emit\" ", 4879 [(callseq_end timm:$amt1, timm:$amt2)]>; 4880 4881// Call subroutine indirectly. 4882let Defs = VolatileV3.Regs in 4883def J2_callr : JUMPR_MISC_CALLR<0, 1>; 4884 4885// Indirect tail-call. 4886let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 4887 isTerminator = 1, isCodeGenOnly = 1 in 4888def TCRETURNr : T_JMPr; 4889 4890// Direct tail-calls. 4891let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 4892 isTerminator = 1, isCodeGenOnly = 1 in 4893def TCRETURNi : JInst<(outs), (ins calltarget:$dst), "", []>; 4894 4895//Tail calls. 4896def: Pat<(HexagonTCRet tglobaladdr:$dst), 4897 (TCRETURNi tglobaladdr:$dst)>; 4898def: Pat<(HexagonTCRet texternalsym:$dst), 4899 (TCRETURNi texternalsym:$dst)>; 4900def: Pat<(HexagonTCRet (i32 IntRegs:$dst)), 4901 (TCRETURNr IntRegs:$dst)>; 4902 4903// Map from r0 = and(r1, 65535) to r0 = zxth(r1) 4904def: Pat<(and (i32 IntRegs:$src1), 65535), 4905 (A2_zxth IntRegs:$src1)>; 4906 4907// Map from r0 = and(r1, 255) to r0 = zxtb(r1). 4908def: Pat<(and (i32 IntRegs:$src1), 255), 4909 (A2_zxtb IntRegs:$src1)>; 4910 4911// Map Add(p1, true) to p1 = not(p1). 4912// Add(p1, false) should never be produced, 4913// if it does, it got to be mapped to NOOP. 4914def: Pat<(add (i1 PredRegs:$src1), -1), 4915 (C2_not PredRegs:$src1)>; 4916 4917// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i). 4918def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3), 4919 (C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>; 4920 4921// Map from p0 = pnot(p0); r0 = select(p0, #i, r1) 4922// => r0 = C2_muxir(p0, r1, #i) 4923def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2, 4924 (i32 IntRegs:$src3)), 4925 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>; 4926 4927// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i) 4928// => r0 = C2_muxri (p0, #i, r1) 4929def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3), 4930 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>; 4931 4932// Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump. 4933def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset), 4934 (J2_jumpf PredRegs:$src1, bb:$offset)>; 4935 4936// Map from Rdd = sign_extend_inreg(Rss, i32) -> Rdd = A2_sxtw(Rss.lo). 4937def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i32)), 4938 (A2_sxtw (LoReg DoubleRegs:$src1))>; 4939 4940// Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = A2_sxtw(A2_sxth(Rss.lo)). 4941def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i16)), 4942 (A2_sxtw (A2_sxth (LoReg DoubleRegs:$src1)))>; 4943 4944// Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = A2_sxtw(A2_sxtb(Rss.lo)). 4945def: Pat<(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)), 4946 (A2_sxtw (A2_sxtb (LoReg DoubleRegs:$src1)))>; 4947 4948// We want to prevent emitting pnot's as much as possible. 4949// Map brcond with an unsupported setcc to a J2_jumpf. 4950def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 4951 bb:$offset), 4952 (J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)), 4953 bb:$offset)>; 4954 4955def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)), 4956 bb:$offset), 4957 (J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>; 4958 4959def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset), 4960 (J2_jumpf PredRegs:$src1, bb:$offset)>; 4961 4962def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset), 4963 (J2_jumpt PredRegs:$src1, bb:$offset)>; 4964 4965// cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1) 4966def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset), 4967 (J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)), 4968 bb:$offset)>; 4969 4970// Map from a 64-bit select to an emulated 64-bit mux. 4971// Hexagon does not support 64-bit MUXes; so emulate with combines. 4972def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2), 4973 (i64 DoubleRegs:$src3)), 4974 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2), 4975 (HiReg DoubleRegs:$src3)), 4976 (C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2), 4977 (LoReg DoubleRegs:$src3)))>; 4978 4979// Map from a 1-bit select to logical ops. 4980// From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3). 4981def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)), 4982 (C2_or (C2_and PredRegs:$src1, PredRegs:$src2), 4983 (C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>; 4984 4985// Map for truncating from 64 immediates to 32 bit immediates. 4986def: Pat<(i32 (trunc (i64 DoubleRegs:$src))), 4987 (LoReg DoubleRegs:$src)>; 4988 4989// Map for truncating from i64 immediates to i1 bit immediates. 4990def: Pat<(i1 (trunc (i64 DoubleRegs:$src))), 4991 (C2_tfrrp (LoReg DoubleRegs:$src))>; 4992 4993// rs <= rt -> !(rs > rt). 4994let AddedComplexity = 30 in 4995def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)), 4996 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>; 4997 4998// rs <= rt -> !(rs > rt). 4999def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 5000 (i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>; 5001 5002// Rss <= Rtt -> !(Rss > Rtt). 5003def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5004 (C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>; 5005 5006// Map cmpne -> cmpeq. 5007// Hexagon_TODO: We should improve on this. 5008// rs != rt -> !(rs == rt). 5009let AddedComplexity = 30 in 5010def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)), 5011 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>; 5012 5013// Convert setne back to xor for hexagon since we compute w/ pred registers. 5014def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))), 5015 (C2_xor PredRegs:$src1, PredRegs:$src2)>; 5016 5017// Map cmpne(Rss) -> !cmpew(Rss). 5018// rs != rt -> !(rs == rt). 5019def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5020 (C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>; 5021 5022// Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt). 5023// rs >= rt -> !(rt > rs). 5024def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))), 5025 (i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>; 5026 5027// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1) 5028let AddedComplexity = 30 in 5029def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)), 5030 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>; 5031 5032// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss). 5033// rss >= rtt -> !(rtt > rss). 5034def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5035 (C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>; 5036 5037// Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm). 5038// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1). 5039// rs < rt -> !(rs >= rt). 5040let AddedComplexity = 30 in 5041def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)), 5042 (C2_not (C2_cmpgti IntRegs:$src1, 5043 (DEC_CONST_SIGNED s32ImmPred:$src2)))>; 5044 5045// Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs) 5046def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)), 5047 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>; 5048 5049// Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1) 5050def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)), 5051 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>; 5052 5053// Generate cmpgtu(Rs, #u9) 5054def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)), 5055 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>; 5056 5057// Map from Rs >= Rt -> !(Rt > Rs). 5058// rs >= rt -> !(rt > rs). 5059def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5060 (C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>; 5061 5062// Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1). 5063// Map from (Rs <= Rt) -> !(Rs > Rt). 5064def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))), 5065 (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>; 5066 5067// Sign extends. 5068// i1 -> i32 5069def: Pat<(i32 (sext (i1 PredRegs:$src1))), 5070 (C2_muxii PredRegs:$src1, -1, 0)>; 5071 5072// i1 -> i64 5073def: Pat<(i64 (sext (i1 PredRegs:$src1))), 5074 (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>; 5075 5076// Zero extends. 5077// i1 -> i32 5078def: Pat<(i32 (zext (i1 PredRegs:$src1))), 5079 (C2_muxii PredRegs:$src1, 1, 0)>; 5080 5081// Map from Rs = Pd to Pd = mux(Pd, #1, #0) 5082def: Pat<(i32 (anyext (i1 PredRegs:$src1))), 5083 (C2_muxii PredRegs:$src1, 1, 0)>; 5084 5085// Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) 5086def: Pat<(i64 (anyext (i1 PredRegs:$src1))), 5087 (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>; 5088 5089// Multiply 64-bit unsigned and use upper result. 5090def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)), 5091 (A2_addp 5092 (M2_dpmpyuu_acc_s0 5093 (S2_lsr_i_p 5094 (A2_addp 5095 (M2_dpmpyuu_acc_s0 5096 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32), 5097 (HiReg $src1), 5098 (LoReg $src2)), 5099 (A2_combinew (A2_tfrsi 0), 5100 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))), 5101 32), 5102 (HiReg $src1), 5103 (HiReg $src2)), 5104 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32) 5105)>; 5106 5107// Hexagon specific ISD nodes. 5108def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 5109 SDTCisVT<1, i32>]>; 5110def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>; 5111 5112def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC", 5113 SDTHexagonADJDYNALLOC>; 5114def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>; 5115 5116// Needed to tag these instructions for stack layout. 5117let isCodeGenOnly = 1, usesCustomInserter = 1 in 5118def ADJDYNALLOC : T_Addri<s6Imm>; 5119 5120def: Pat<(Hexagon_ADJDYNALLOC I32:$Rs, s16ImmPred:$s16), 5121 (ADJDYNALLOC I32:$Rs, imm:$s16)>; 5122 5123let isCodeGenOnly = 1 in 5124def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1), 5125 "$dst = $src1", 5126 [(set (i32 IntRegs:$dst), 5127 (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>; 5128 5129let AddedComplexity = 100 in 5130def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)), 5131 (i32 IntRegs:$src1)>; 5132 5133def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>; 5134def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>; 5135 5136def: Pat<(HexagonJT tjumptable:$dst), 5137 (CONST32_set_jt tjumptable:$dst)>; 5138def: Pat<(HexagonCP tconstpool :$dst), 5139 (CONST32_set_jt tconstpool:$dst)>; 5140 5141// XTYPE/SHIFT 5142// 5143//===----------------------------------------------------------------------===// 5144// Template Class 5145// Shift by immediate/register and accumulate/logical 5146//===----------------------------------------------------------------------===// 5147 5148// Rx[+-&|]=asr(Rs,#u5) 5149// Rx[+-&|^]=lsr(Rs,#u5) 5150// Rx[+-&|^]=asl(Rs,#u5) 5151 5152let hasNewValue = 1, opNewValue = 0 in 5153class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1, 5154 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5155 : SInst_acc<(outs IntRegs:$Rx), 5156 (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5), 5157 "$Rx "#opc2#opc1#"($Rs, #$u5)", 5158 [(set (i32 IntRegs:$Rx), 5159 (OpNode2 (i32 IntRegs:$src1), 5160 (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))], 5161 "$src1 = $Rx", S_2op_tc_2_SLOT23> { 5162 bits<5> Rx; 5163 bits<5> Rs; 5164 bits<5> u5; 5165 5166 let IClass = 0b1000; 5167 5168 let Inst{27-24} = 0b1110; 5169 let Inst{23-22} = majOp{2-1}; 5170 let Inst{13} = 0b0; 5171 let Inst{7} = majOp{0}; 5172 let Inst{6-5} = minOp; 5173 let Inst{4-0} = Rx; 5174 let Inst{20-16} = Rs; 5175 let Inst{12-8} = u5; 5176 } 5177 5178// Rx[+-&|]=asr(Rs,Rt) 5179// Rx[+-&|^]=lsr(Rs,Rt) 5180// Rx[+-&|^]=asl(Rs,Rt) 5181 5182let hasNewValue = 1, opNewValue = 0 in 5183class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1, 5184 SDNode OpNode2, bits<2> majOp, bits<2> minOp> 5185 : SInst_acc<(outs IntRegs:$Rx), 5186 (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt), 5187 "$Rx "#opc2#opc1#"($Rs, $Rt)", 5188 [(set (i32 IntRegs:$Rx), 5189 (OpNode2 (i32 IntRegs:$src1), 5190 (OpNode1 (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))], 5191 "$src1 = $Rx", S_3op_tc_2_SLOT23 > { 5192 bits<5> Rx; 5193 bits<5> Rs; 5194 bits<5> Rt; 5195 5196 let IClass = 0b1100; 5197 5198 let Inst{27-24} = 0b1100; 5199 let Inst{23-22} = majOp; 5200 let Inst{7-6} = minOp; 5201 let Inst{4-0} = Rx; 5202 let Inst{20-16} = Rs; 5203 let Inst{12-8} = Rt; 5204 } 5205 5206// Rxx[+-&|]=asr(Rss,#u6) 5207// Rxx[+-&|^]=lsr(Rss,#u6) 5208// Rxx[+-&|^]=asl(Rss,#u6) 5209 5210class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1, 5211 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5212 : SInst_acc<(outs DoubleRegs:$Rxx), 5213 (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6), 5214 "$Rxx "#opc2#opc1#"($Rss, #$u6)", 5215 [(set (i64 DoubleRegs:$Rxx), 5216 (OpNode2 (i64 DoubleRegs:$src1), 5217 (OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))], 5218 "$src1 = $Rxx", S_2op_tc_2_SLOT23> { 5219 bits<5> Rxx; 5220 bits<5> Rss; 5221 bits<6> u6; 5222 5223 let IClass = 0b1000; 5224 5225 let Inst{27-24} = 0b0010; 5226 let Inst{23-22} = majOp{2-1}; 5227 let Inst{7} = majOp{0}; 5228 let Inst{6-5} = minOp; 5229 let Inst{4-0} = Rxx; 5230 let Inst{20-16} = Rss; 5231 let Inst{13-8} = u6; 5232 } 5233 5234 5235// Rxx[+-&|]=asr(Rss,Rt) 5236// Rxx[+-&|^]=lsr(Rss,Rt) 5237// Rxx[+-&|^]=asl(Rss,Rt) 5238// Rxx[+-&|^]=lsl(Rss,Rt) 5239 5240class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1, 5241 SDNode OpNode2, bits<3> majOp, bits<2> minOp> 5242 : SInst_acc<(outs DoubleRegs:$Rxx), 5243 (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt), 5244 "$Rxx "#opc2#opc1#"($Rss, $Rt)", 5245 [(set (i64 DoubleRegs:$Rxx), 5246 (OpNode2 (i64 DoubleRegs:$src1), 5247 (OpNode1 (i64 DoubleRegs:$Rss), (i32 IntRegs:$Rt))))], 5248 "$src1 = $Rxx", S_3op_tc_2_SLOT23> { 5249 bits<5> Rxx; 5250 bits<5> Rss; 5251 bits<5> Rt; 5252 5253 let IClass = 0b1100; 5254 5255 let Inst{27-24} = 0b1011; 5256 let Inst{23-21} = majOp; 5257 let Inst{20-16} = Rss; 5258 let Inst{12-8} = Rt; 5259 let Inst{7-6} = minOp; 5260 let Inst{4-0} = Rxx; 5261 } 5262 5263//===----------------------------------------------------------------------===// 5264// Multi-class for the shift instructions with logical/arithmetic operators. 5265//===----------------------------------------------------------------------===// 5266 5267multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1, 5268 SDNode OpNode2, bits<3> majOp, bits<2> minOp > { 5269 def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1, 5270 OpNode2, majOp, minOp >; 5271 def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1, 5272 OpNode2, majOp, minOp >; 5273} 5274 5275multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { 5276 let AddedComplexity = 100 in 5277 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>; 5278 5279 defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>; 5280 defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>; 5281 defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>; 5282} 5283 5284multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { 5285let AddedComplexity = 100 in 5286 defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>; 5287} 5288 5289defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>; 5290 5291defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>, 5292 xtype_xor_imm_acc<"lsr", srl, 0b01>; 5293 5294defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>, 5295 xtype_xor_imm_acc<"asl", shl, 0b10>; 5296 5297multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> { 5298 let AddedComplexity = 100 in 5299 def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>; 5300 5301 def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>; 5302 def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>; 5303 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>; 5304} 5305 5306multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> { 5307 let AddedComplexity = 100 in 5308 def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>; 5309 5310 def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>; 5311 def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>; 5312 def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>; 5313 def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>; 5314} 5315 5316multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > { 5317 defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>; 5318 defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>; 5319} 5320 5321defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>; 5322defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>; 5323defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>; 5324defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>; 5325 5326//===----------------------------------------------------------------------===// 5327let hasSideEffects = 0 in 5328class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp, 5329 bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0> 5330 : SInst <(outs RC:$dst), 5331 (ins DoubleRegs:$src1, DoubleRegs:$src2), 5332 "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "") 5333 #!if(hasShift,":>>1","") 5334 #!if(isSat, ":sat", ""), 5335 [], "", S_3op_tc_2_SLOT23 > { 5336 bits<5> dst; 5337 bits<5> src1; 5338 bits<5> src2; 5339 5340 let IClass = 0b1100; 5341 5342 let Inst{27-24} = 0b0001; 5343 let Inst{23-22} = MajOp; 5344 let Inst{20-16} = !if (SwapOps, src2, src1); 5345 let Inst{12-8} = !if (SwapOps, src1, src2); 5346 let Inst{7-5} = MinOp; 5347 let Inst{4-0} = dst; 5348 } 5349 5350class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps, 5351 bit isSat = 0, bit isRnd = 0, bit hasShift = 0 > 5352 : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps, 5353 isSat, isRnd, hasShift>; 5354 5355let Itinerary = S_3op_tc_1_SLOT23 in { 5356 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>; 5357 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>; 5358 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>; 5359 def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>; 5360 5361 def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>; 5362 def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>; 5363} 5364 5365def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; 5366 5367let hasSideEffects = 0 in 5368class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps> 5369 : SInst < (outs DoubleRegs:$Rdd), 5370 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), 5371 "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)", 5372 [], "", S_3op_tc_1_SLOT23 > { 5373 bits<5> Rdd; 5374 bits<5> Rss; 5375 bits<5> Rtt; 5376 bits<2> Pu; 5377 5378 let IClass = 0b1100; 5379 5380 let Inst{27-24} = 0b0010; 5381 let Inst{23-21} = MajOp; 5382 let Inst{20-16} = !if (SwapOps, Rtt, Rss); 5383 let Inst{12-8} = !if (SwapOps, Rss, Rtt); 5384 let Inst{6-5} = Pu; 5385 let Inst{4-0} = Rdd; 5386 } 5387 5388def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>; 5389def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>; 5390 5391//===----------------------------------------------------------------------===// 5392// Template class used by vector shift, vector rotate, vector neg, 5393// 32-bit shift, 64-bit shifts, etc. 5394//===----------------------------------------------------------------------===// 5395 5396let hasSideEffects = 0 in 5397class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp, 5398 bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] > 5399 : SInst <(outs RC:$dst), 5400 (ins RC:$src1, IntRegs:$src2), 5401 "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""), 5402 pattern, "", S_3op_tc_1_SLOT23> { 5403 bits<5> dst; 5404 bits<5> src1; 5405 bits<5> src2; 5406 5407 let IClass = 0b1100; 5408 5409 let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011); 5410 let Inst{23-22} = MajOp; 5411 let Inst{20-16} = src1; 5412 let Inst{12-8} = src2; 5413 let Inst{7-6} = MinOp; 5414 let Inst{4-0} = dst; 5415 } 5416 5417let hasNewValue = 1 in 5418class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp> 5419 : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0, 5420 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1), 5421 (i32 IntRegs:$src2)))]>; 5422 5423let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in 5424class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp> 5425 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>; 5426 5427 5428class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp> 5429 : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0, 5430 [(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1), 5431 (i32 IntRegs:$src2)))]>; 5432 5433 5434class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp> 5435 : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>; 5436 5437 5438// Shift by register 5439// Rdd=[asr|lsr|asl|lsl](Rss,Rt) 5440 5441def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>; 5442def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>; 5443def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>; 5444def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>; 5445 5446// Rd=[asr|lsr|asl|lsl](Rs,Rt) 5447 5448def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>; 5449def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>; 5450def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>; 5451def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>; 5452 5453// Shift by register with saturation 5454// Rd=asr(Rs,Rt):sat 5455// Rd=asl(Rs,Rt):sat 5456 5457let Defs = [USR_OVF] in { 5458 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>; 5459 def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; 5460} 5461 5462let hasNewValue = 1, hasSideEffects = 0 in 5463class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0> 5464 : SInst < (outs IntRegs:$Rd), 5465 (ins DoubleRegs:$Rss, IntRegs:$Rt), 5466 "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")" 5467 #!if(hasShift, ":<<1", "") 5468 #!if(isRnd, ":rnd", "") 5469 #!if(isSat, ":sat", ""), 5470 [], "", S_3op_tc_1_SLOT23 > { 5471 bits<5> Rd; 5472 bits<5> Rss; 5473 bits<5> Rt; 5474 5475 let IClass = 0b1100; 5476 5477 let Inst{27-24} = 0b0101; 5478 let Inst{20-16} = Rss; 5479 let Inst{12-8} = Rt; 5480 let Inst{7-5} = MinOp; 5481 let Inst{4-0} = Rd; 5482 } 5483 5484def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>; 5485 5486let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in 5487def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; 5488 5489let hasSideEffects = 0 in 5490class T_S3op_7 <string mnemonic, bit MajOp > 5491 : SInst <(outs DoubleRegs:$Rdd), 5492 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3), 5493 "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" , 5494 [], "", S_3op_tc_1_SLOT23 > { 5495 bits<5> Rdd; 5496 bits<5> Rss; 5497 bits<5> Rtt; 5498 bits<3> u3; 5499 5500 let IClass = 0b1100; 5501 5502 let Inst{27-24} = 0b0000; 5503 let Inst{23} = MajOp; 5504 let Inst{20-16} = !if(MajOp, Rss, Rtt); 5505 let Inst{12-8} = !if(MajOp, Rtt, Rss); 5506 let Inst{7-5} = u3; 5507 let Inst{4-0} = Rdd; 5508 } 5509 5510def S2_valignib : T_S3op_7 < "valignb", 0>; 5511def S2_vspliceib : T_S3op_7 < "vspliceb", 1>; 5512 5513//===----------------------------------------------------------------------===// 5514// Template class for 'insert bitfield' instructions 5515//===----------------------------------------------------------------------===// 5516let hasSideEffects = 0 in 5517class T_S3op_insert <string mnemonic, RegisterClass RC> 5518 : SInst <(outs RC:$dst), 5519 (ins RC:$src1, RC:$src2, DoubleRegs:$src3), 5520 "$dst = "#mnemonic#"($src2, $src3)" , 5521 [], "$src1 = $dst", S_3op_tc_1_SLOT23 > { 5522 bits<5> dst; 5523 bits<5> src2; 5524 bits<5> src3; 5525 5526 let IClass = 0b1100; 5527 5528 let Inst{27-26} = 0b10; 5529 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10); 5530 let Inst{23} = 0b0; 5531 let Inst{20-16} = src2; 5532 let Inst{12-8} = src3; 5533 let Inst{4-0} = dst; 5534 } 5535 5536let hasSideEffects = 0 in 5537class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp> 5538 : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3), 5539 "$dst = insert($src1, #$src2, #$src3)", 5540 [], "$dst2 = $dst", S_2op_tc_2_SLOT23> { 5541 bits<5> dst; 5542 bits<5> src1; 5543 bits<6> src2; 5544 bits<6> src3; 5545 bit bit23; 5546 bit bit13; 5547 string ImmOpStr = !cast<string>(ImmOp); 5548 5549 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0); 5550 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0); 5551 5552 let IClass = 0b1000; 5553 5554 let Inst{27-24} = RegTyBits; 5555 let Inst{23} = bit23; 5556 let Inst{22-21} = src3{4-3}; 5557 let Inst{20-16} = src1; 5558 let Inst{13} = bit13; 5559 let Inst{12-8} = src2{4-0}; 5560 let Inst{7-5} = src3{2-0}; 5561 let Inst{4-0} = dst; 5562 } 5563 5564// Rx=insert(Rs,Rtt) 5565// Rx=insert(Rs,#u5,#U5) 5566let hasNewValue = 1 in { 5567 def S2_insert_rp : T_S3op_insert <"insert", IntRegs>; 5568 def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>; 5569} 5570 5571// Rxx=insert(Rss,Rtt) 5572// Rxx=insert(Rss,#u6,#U6) 5573def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>; 5574def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>; 5575 5576 5577def SDTHexagonINSERT_ri : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, 5578 SDTCisVT<1, i32>, 5579 SDTCisVT<2, i32>, 5580 SDTCisVT<3, i32>, 5581 SDTCisVT<4, i32>]>; 5582def SDTHexagonINSERT_rd : SDTypeProfile<1, 4, [SDTCisVT<0, i64>, 5583 SDTCisVT<1, i64>, 5584 SDTCisVT<2, i64>, 5585 SDTCisVT<3, i32>, 5586 SDTCisVT<4, i32>]>; 5587def SDTHexagonINSERT_riv : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 5588 SDTCisVT<1, i32>, 5589 SDTCisVT<2, i32>, 5590 SDTCisVT<3, i64>]>; 5591def SDTHexagonINSERT_rdv : SDTypeProfile<1, 3, [SDTCisVT<0, i64>, 5592 SDTCisVT<1, i64>, 5593 SDTCisVT<2, i64>, 5594 SDTCisVT<3, i64>]>; 5595def HexagonINSERT_ri : SDNode<"HexagonISD::INSERT_ri", SDTHexagonINSERT_ri>; 5596def HexagonINSERT_rd : SDNode<"HexagonISD::INSERT_rd", SDTHexagonINSERT_rd>; 5597def HexagonINSERT_riv: SDNode<"HexagonISD::INSERT_riv", SDTHexagonINSERT_riv>; 5598def HexagonINSERT_rdv: SDNode<"HexagonISD::INSERT_rdv", SDTHexagonINSERT_rdv>; 5599 5600def: Pat<(HexagonINSERT_ri I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2), 5601 (S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>; 5602 5603def: Pat<(HexagonINSERT_rd I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2), 5604 (S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>; 5605 5606def: Pat<(HexagonINSERT_riv I32:$Rs, I32:$Rt, I64:$Ru), 5607 (S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>; 5608 5609def: Pat<(HexagonINSERT_rdv I64:$Rs, I64:$Rt, I64:$Ru), 5610 (S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>; 5611 5612 5613//===----------------------------------------------------------------------===// 5614// Template class for 'extract bitfield' instructions 5615//===----------------------------------------------------------------------===// 5616let hasNewValue = 1, hasSideEffects = 0 in 5617class T_S3op_extract <string mnemonic, bits<2> MinOp> 5618 : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), 5619 "$Rd = "#mnemonic#"($Rs, $Rtt)", 5620 [], "", S_3op_tc_2_SLOT23 > { 5621 bits<5> Rd; 5622 bits<5> Rs; 5623 bits<5> Rtt; 5624 5625 let IClass = 0b1100; 5626 5627 let Inst{27-22} = 0b100100; 5628 let Inst{20-16} = Rs; 5629 let Inst{12-8} = Rtt; 5630 let Inst{7-6} = MinOp; 5631 let Inst{4-0} = Rd; 5632 } 5633 5634let hasSideEffects = 0 in 5635class T_S2op_extract <string mnemonic, bits<4> RegTyBits, 5636 RegisterClass RC, Operand ImmOp> 5637 : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3), 5638 "$dst = "#mnemonic#"($src1, #$src2, #$src3)", 5639 [], "", S_2op_tc_2_SLOT23> { 5640 bits<5> dst; 5641 bits<5> src1; 5642 bits<6> src2; 5643 bits<6> src3; 5644 bit bit23; 5645 bit bit13; 5646 string ImmOpStr = !cast<string>(ImmOp); 5647 5648 let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 5649 !if (!eq(mnemonic, "extractu"), 0, 1)); 5650 5651 let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0); 5652 5653 let IClass = 0b1000; 5654 5655 let Inst{27-24} = RegTyBits; 5656 let Inst{23} = bit23; 5657 let Inst{22-21} = src3{4-3}; 5658 let Inst{20-16} = src1; 5659 let Inst{13} = bit13; 5660 let Inst{12-8} = src2{4-0}; 5661 let Inst{7-5} = src3{2-0}; 5662 let Inst{4-0} = dst; 5663 } 5664 5665// Extract bitfield 5666 5667// Rdd=extractu(Rss,Rtt) 5668// Rdd=extractu(Rss,#u6,#U6) 5669def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>; 5670def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>; 5671 5672// Rd=extractu(Rs,Rtt) 5673// Rd=extractu(Rs,#u5,#U5) 5674let hasNewValue = 1 in { 5675 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>; 5676 def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>; 5677} 5678 5679def SDTHexagonEXTRACTU_ri : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 5680 SDTCisVT<1, i32>, 5681 SDTCisVT<2, i32>, 5682 SDTCisVT<3, i32>]>; 5683def SDTHexagonEXTRACTU_rd : SDTypeProfile<1, 3, [SDTCisVT<0, i64>, 5684 SDTCisVT<1, i64>, 5685 SDTCisVT<2, i32>, 5686 SDTCisVT<3, i32>]>; 5687def SDTHexagonEXTRACTU_riv : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 5688 SDTCisVT<1, i32>, 5689 SDTCisVT<2, i64>]>; 5690def SDTHexagonEXTRACTU_rdv : SDTypeProfile<1, 2, [SDTCisVT<0, i64>, 5691 SDTCisVT<1, i64>, 5692 SDTCisVT<2, i64>]>; 5693def HexagonEXTRACTU_ri : SDNode<"HexagonISD::EXTRACTU_ri", SDTHexagonEXTRACTU_ri>; 5694def HexagonEXTRACTU_rd : SDNode<"HexagonISD::EXTRACTU_rd", SDTHexagonEXTRACTU_rd>; 5695def HexagonEXTRACTU_riv: SDNode<"HexagonISD::EXTRACTU_riv", SDTHexagonEXTRACTU_riv>; 5696def HexagonEXTRACTU_rdv: SDNode<"HexagonISD::EXTRACTU_rdv", SDTHexagonEXTRACTU_rdv>; 5697 5698def: Pat<(HexagonEXTRACTU_ri I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3), 5699 (S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>; 5700 5701def: Pat<(HexagonEXTRACTU_rd I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3), 5702 (S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>; 5703 5704def: Pat<(HexagonEXTRACTU_riv I32:$src1, I64:$src2), 5705 (S2_extractu_rp I32:$src1, I64:$src2)>; 5706 5707def: Pat<(HexagonEXTRACTU_rdv I64:$src1, I64:$src2), 5708 (S2_extractup_rp I64:$src1, I64:$src2)>; 5709 5710// Change the sign of the immediate for Rd=-mpyi(Rs,#u8) 5711def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)), 5712 (M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>; 5713 5714//===----------------------------------------------------------------------===// 5715// :raw for of tableindx[bdhw] insns 5716//===----------------------------------------------------------------------===// 5717 5718let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 5719class tableidxRaw<string OpStr, bits<2>MinOp> 5720 : SInst <(outs IntRegs:$Rx), 5721 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6), 5722 "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw", 5723 [], "$Rx = $_dst_" > { 5724 bits<5> Rx; 5725 bits<5> Rs; 5726 bits<4> u4; 5727 bits<6> S6; 5728 5729 let IClass = 0b1000; 5730 5731 let Inst{27-24} = 0b0111; 5732 let Inst{23-22} = MinOp; 5733 let Inst{21} = u4{3}; 5734 let Inst{20-16} = Rs; 5735 let Inst{13-8} = S6; 5736 let Inst{7-5} = u4{2-0}; 5737 let Inst{4-0} = Rx; 5738 } 5739 5740def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>; 5741def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>; 5742def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>; 5743def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>; 5744 5745//===----------------------------------------------------------------------===// 5746// Template class for 'table index' instructions which are assembler mapped 5747// to their :raw format. 5748//===----------------------------------------------------------------------===// 5749let isPseudo = 1 in 5750class tableidx_goodsyntax <string mnemonic> 5751 : SInst <(outs IntRegs:$Rx), 5752 (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5), 5753 "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)", 5754 [], "$Rx = $_dst_" >; 5755 5756def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">; 5757def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">; 5758def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">; 5759def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">; 5760 5761//===----------------------------------------------------------------------===// 5762// V3 Instructions + 5763//===----------------------------------------------------------------------===// 5764 5765include "HexagonInstrInfoV3.td" 5766 5767//===----------------------------------------------------------------------===// 5768// V3 Instructions - 5769//===----------------------------------------------------------------------===// 5770 5771//===----------------------------------------------------------------------===// 5772// V4 Instructions + 5773//===----------------------------------------------------------------------===// 5774 5775include "HexagonInstrInfoV4.td" 5776 5777//===----------------------------------------------------------------------===// 5778// V4 Instructions - 5779//===----------------------------------------------------------------------===// 5780 5781//===----------------------------------------------------------------------===// 5782// V5 Instructions + 5783//===----------------------------------------------------------------------===// 5784 5785include "HexagonInstrInfoV5.td" 5786 5787//===----------------------------------------------------------------------===// 5788// V5 Instructions - 5789//===----------------------------------------------------------------------===// 5790 5791//===----------------------------------------------------------------------===// 5792// ALU32/64/Vector + 5793//===----------------------------------------------------------------------===/// 5794 5795include "HexagonInstrInfoVector.td" 5796