Lines Matching refs:u5

4044   (ins RCIn:$src, u5Imm:$u5),
4045   "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
4050     bits<5> u5;
4058     let Inst{12-8} = u5;
4079                                     (u5ImmPred:$u5)))]>;
4100   : SInst <(outs IntRegs:$dst), (ins  IntRegs:$src, u5Imm:$u5),
4101   "$dst = asrrnd($src, #$u5)",
4205     : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
4206             "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
4209   bits<5> u5;
4214   let Inst{12-8} = u5;
4241 def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
4242          (S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4243 def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4244          (S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4245 def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
4246          (S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
4258     : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
4259             "$Pd = "#MnOp#"($Rs, #$u5)",
4263   bits<5> u5;
4269   let Inst{12-8} = u5;
4293   def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
4294            (S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
5148 // Rx[+-&|]=asr(Rs,#u5)
5149 // Rx[+-&|^]=lsr(Rs,#u5)
5150 // Rx[+-&|^]=asl(Rs,#u5)
5156               (ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
5157   "$Rx "#opc2#opc1#"($Rs, #$u5)",
5160                   (OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
5164     bits<5> u5;
5175     let Inst{12-8} = u5;
5565 // Rx=insert(Rs,#u5,#U5)
5673 // Rd=extractu(Rs,#u5,#U5)
5752            (ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),
5753            "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",