Lines Matching refs:addr
22 %__a.addr.i31 = alloca i32, align 4
23 %__b.addr.i32 = alloca <4 x i32>*, align 8
24 %__a.addr.i29 = alloca i32, align 4
25 %__b.addr.i30 = alloca <4 x float>*, align 8
26 %__a.addr.i27 = alloca i32, align 4
27 %__b.addr.i28 = alloca <2 x i64>*, align 8
28 %__a.addr.i25 = alloca i32, align 4
29 %__b.addr.i26 = alloca <2 x i64>*, align 8
30 %__a.addr.i23 = alloca i32, align 4
31 %__b.addr.i24 = alloca <2 x double>*, align 8
32 %__a.addr.i20 = alloca <4 x i32>, align 16
33 %__b.addr.i21 = alloca i32, align 4
34 %__c.addr.i22 = alloca <4 x i32>*, align 8
35 %__a.addr.i17 = alloca <4 x i32>, align 16
36 %__b.addr.i18 = alloca i32, align 4
37 %__c.addr.i19 = alloca <4 x i32>*, align 8
38 %__a.addr.i14 = alloca <4 x float>, align 16
39 %__b.addr.i15 = alloca i32, align 4
40 %__c.addr.i16 = alloca <4 x float>*, align 8
41 %__a.addr.i11 = alloca <2 x i64>, align 16
42 %__b.addr.i12 = alloca i32, align 4
43 %__c.addr.i13 = alloca <2 x i64>*, align 8
44 %__a.addr.i8 = alloca <2 x i64>, align 16
45 %__b.addr.i9 = alloca i32, align 4
46 %__c.addr.i10 = alloca <2 x i64>*, align 8
47 %__a.addr.i6 = alloca <2 x double>, align 16
48 %__b.addr.i7 = alloca i32, align 4
49 %__c.addr.i = alloca <2 x double>*, align 8
50 %__a.addr.i = alloca i32, align 4
51 %__b.addr.i = alloca <4 x i32>*, align 8
52 store i32 0, i32* %__a.addr.i, align 4
53 store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8
54 %0 = load i32, i32* %__a.addr.i, align 4
55 %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
60 store i32 0, i32* %__a.addr.i31, align 4
61 store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8
62 %5 = load i32, i32* %__a.addr.i31, align 4
63 %6 = load <4 x i32>*, <4 x i32>** %__b.addr.i32, align 8
68 store i32 0, i32* %__a.addr.i29, align 4
69 store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8
70 %10 = load i32, i32* %__a.addr.i29, align 4
71 %11 = load <4 x float>*, <4 x float>** %__b.addr.i30, align 8
77 store i32 0, i32* %__a.addr.i27, align 4
78 store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8
79 %16 = load i32, i32* %__a.addr.i27, align 4
80 %17 = load <2 x i64>*, <2 x i64>** %__b.addr.i28, align 8
86 store i32 0, i32* %__a.addr.i25, align 4
87 store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8
88 %22 = load i32, i32* %__a.addr.i25, align 4
89 %23 = load <2 x i64>*, <2 x i64>** %__b.addr.i26, align 8
95 store i32 0, i32* %__a.addr.i23, align 4
96 store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8
97 %28 = load i32, i32* %__a.addr.i23, align 4
98 %29 = load <2 x double>*, <2 x double>** %__b.addr.i24, align 8
104 store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16
105 store i32 0, i32* %__b.addr.i21, align 4
106 store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8
107 %34 = load <4 x i32>, <4 x i32>* %__a.addr.i20, align 16
108 %35 = load i32, i32* %__b.addr.i21, align 4
109 %36 = load <4 x i32>*, <4 x i32>** %__c.addr.i22, align 8
114 store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16
115 store i32 0, i32* %__b.addr.i18, align 4
116 store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8
117 %40 = load <4 x i32>, <4 x i32>* %__a.addr.i17, align 16
118 %41 = load i32, i32* %__b.addr.i18, align 4
119 %42 = load <4 x i32>*, <4 x i32>** %__c.addr.i19, align 8
124 store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16
125 store i32 0, i32* %__b.addr.i15, align 4
126 store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8
127 %46 = load <4 x float>, <4 x float>* %__a.addr.i14, align 16
129 %48 = load i32, i32* %__b.addr.i15, align 4
130 %49 = load <4 x float>*, <4 x float>** %__c.addr.i16, align 8
135 store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16
136 store i32 0, i32* %__b.addr.i12, align 4
137 store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8
138 %53 = load <2 x i64>, <2 x i64>* %__a.addr.i11, align 16
140 %55 = load i32, i32* %__b.addr.i12, align 4
141 %56 = load <2 x i64>*, <2 x i64>** %__c.addr.i13, align 8
146 store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16
147 store i32 0, i32* %__b.addr.i9, align 4
148 store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8
149 %60 = load <2 x i64>, <2 x i64>* %__a.addr.i8, align 16
151 %62 = load i32, i32* %__b.addr.i9, align 4
152 %63 = load <2 x i64>*, <2 x i64>** %__c.addr.i10, align 8
157 store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16
158 store i32 0, i32* %__b.addr.i7, align 4
159 store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8
160 %67 = load <2 x double>, <2 x double>* %__a.addr.i6, align 16
161 %68 = load i32, i32* %__b.addr.i7, align 4
162 %69 = load <2 x double>*, <2 x double>** %__c.addr.i, align 8