| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 94 bool IsStore, IsLoad; in runOnFunction() local
152 bool IsStore, bool IsLoad) { in bracketInstWithFences()
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| D | InlineSpiller.cpp | 1018 bool IsLoad = InstrReg; in coalesceStackAccess() local
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| /external/v8/src/arm64/ |
| D | instructions-arm64.cc | 18 bool Instruction::IsLoad() const { in IsLoad() function in v8::internal::Instruction
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | CheckerDocumentation.cpp | 128 void checkLocation(SVal Loc, bool IsLoad, const Stmt *S, in checkLocation()
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| /external/llvm/lib/Target/R600/ |
| D | SIRegisterInfo.cpp | 151 bool IsLoad = TII->get(LoadStoreOp).mayLoad(); in buildScratchLoadStore() local
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| /external/vixl/src/vixl/a64/ |
| D | instructions-a64.cc | 74 bool Instruction::IsLoad() const { in IsLoad() function in vixl::Instruction
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1062 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodeSignedLdStInstruction() local
1163 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodePairLdStInstruction() local
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| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.cpp | 426 void DecodeScalarMoveMask(MVT VT, bool IsLoad, SmallVectorImpl<int> &Mask) { in DecodeScalarMoveMask()
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| /external/clang/include/clang/StaticAnalyzer/Core/ |
| D | Checker.h | 514 bool IsLoad; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 107 bool IsLoad; member
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| D | ARMLoadStoreOptimizer.cpp | 392 bool IsLoad = in UpdateBaseRegUses() local
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| D | ARMISelDAGToDAG.cpp | 2052 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, in SelectVLDSTLane()
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| /external/v8/src/compiler/ |
| D | graph-unittest.cc | 718 Matcher<Node*> IsLoad(const Matcher<LoadRepresentation>& rep_matcher, in IsLoad() function
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 924 bool IsLoad = E->getOp() == AtomicExpr::AO__c11_atomic_load || in EmitAtomicExpr() local
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | CheckerManager.cpp | 266 bool IsLoad; member
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 844 bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore(); in canMoveMemTo() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1056 bool IsStore, bool IsLoad) const { in emitLeadingFence()
1067 bool IsStore, bool IsLoad) const { in emitTrailingFence()
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| /external/v8/src/ |
| D | hydrogen.h | 2474 bool IsLoad() const { return access_type_ == LOAD; } in IsLoad() function
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 13292 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile(); in GatherAllAliases() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4999 bool IsLoad = ISD::isNormalLoad(Ld.getNode()); in LowerVectorBroadcast() local
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