1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Disassembler.h"
14 #include "AArch64ExternalSymbolizer.h"
15 #include "AArch64Subtarget.h"
16 #include "MCTargetDesc/AArch64AddressingModes.h"
17 #include "Utils/AArch64BaseInfo.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "aarch64-disassembler"
27 
28 // Pull DecodeStatus and its enum values into the global namespace.
29 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
30 
31 // Forward declare these because the autogenerated code will reference them.
32 // Definitions are further down.
33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
34                                               unsigned RegNo, uint64_t Address,
35                                               const void *Decoder);
36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
37                                                  unsigned RegNo,
38                                                  uint64_t Address,
39                                                  const void *Decoder);
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
41                                              uint64_t Address,
42                                              const void *Decoder);
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
44                                              uint64_t Address,
45                                              const void *Decoder);
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
47                                              uint64_t Address,
48                                              const void *Decoder);
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50                                             uint64_t Address,
51                                             const void *Decoder);
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
53                                              uint64_t Address,
54                                              const void *Decoder);
55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
56                                                unsigned RegNo, uint64_t Address,
57                                                const void *Decoder);
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
59                                              uint64_t Address,
60                                              const void *Decoder);
61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
62                                                unsigned RegNo, uint64_t Address,
63                                                const void *Decoder);
64 static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
65                                           uint64_t Address,
66                                           const void *Decoder);
67 static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
68                                            uint64_t Address,
69                                            const void *Decoder);
70 static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
71                                             uint64_t Address,
72                                             const void *Decoder);
73 static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
74                                           uint64_t Address,
75                                           const void *Decoder);
76 static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
77                                            uint64_t Address,
78                                            const void *Decoder);
79 static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
80                                             uint64_t Address,
81                                             const void *Decoder);
82 
83 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
84                                                uint64_t Address,
85                                                const void *Decoder);
86 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
87                                                uint64_t Address,
88                                                const void *Decoder);
89 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
90                                        uint64_t Address, const void *Decoder);
91 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
92                                     uint64_t Address, const void *Decoder);
93 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
94                                             uint64_t Address, const void *Decoder);
95 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
96                                             uint64_t Address, const void *Decoder);
97 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
98                                                    uint32_t insn,
99                                                    uint64_t Address,
100                                                    const void *Decoder);
101 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
102                                              uint64_t Address,
103                                              const void *Decoder);
104 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
105                                                   uint32_t insn,
106                                                   uint64_t Address,
107                                                   const void *Decoder);
108 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
109                                                 uint32_t insn, uint64_t Address,
110                                                 const void *Decoder);
111 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
112                                                    uint32_t insn,
113                                                    uint64_t Address,
114                                                    const void *Decoder);
115 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
116                                               uint64_t Address,
117                                               const void *Decoder);
118 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
119                                                 uint32_t insn, uint64_t Address,
120                                                 const void *Decoder);
121 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
122                                                 uint32_t insn, uint64_t Address,
123                                                 const void *Decoder);
124 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
125                                             uint64_t Address,
126                                             const void *Decoder);
127 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
128                                                 uint32_t insn, uint64_t Address,
129                                                 const void *Decoder);
130 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
131                                          uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
133                                         uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
135                                               uint64_t Address,
136                                               const void *Decoder);
137 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
138                                                   uint32_t insn,
139                                                   uint64_t Address,
140                                                   const void *Decoder);
141 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
142                                         uint64_t Address, const void *Decoder);
143 
144 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
145                                               uint64_t Address,
146                                               const void *Decoder);
147 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
148                                          uint64_t Addr, const void *Decoder);
149 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
150                                                uint64_t Addr,
151                                                const void *Decoder);
152 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
153                                          uint64_t Addr, const void *Decoder);
154 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
155                                                uint64_t Addr,
156                                                const void *Decoder);
157 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
158                                          uint64_t Addr, const void *Decoder);
159 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
160                                                uint64_t Addr,
161                                                const void *Decoder);
162 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
163                                         uint64_t Addr, const void *Decoder);
164 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
165                                          uint64_t Addr, const void *Decoder);
166 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
167                                          uint64_t Addr, const void *Decoder);
168 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
169                                          uint64_t Addr, const void *Decoder);
170 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
171                                         uint64_t Addr, const void *Decoder);
172 
Check(DecodeStatus & Out,DecodeStatus In)173 static bool Check(DecodeStatus &Out, DecodeStatus In) {
174   switch (In) {
175     case MCDisassembler::Success:
176       // Out stays the same.
177       return true;
178     case MCDisassembler::SoftFail:
179       Out = In;
180       return true;
181     case MCDisassembler::Fail:
182       Out = In;
183       return false;
184   }
185   llvm_unreachable("Invalid DecodeStatus!");
186 }
187 
188 #include "AArch64GenDisassemblerTables.inc"
189 #include "AArch64GenInstrInfo.inc"
190 
191 #define Success llvm::MCDisassembler::Success
192 #define Fail llvm::MCDisassembler::Fail
193 #define SoftFail llvm::MCDisassembler::SoftFail
194 
createAArch64Disassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)195 static MCDisassembler *createAArch64Disassembler(const Target &T,
196                                                const MCSubtargetInfo &STI,
197                                                MCContext &Ctx) {
198   return new AArch64Disassembler(STI, Ctx);
199 }
200 
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & OS,raw_ostream & CS) const201 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
202                                                  ArrayRef<uint8_t> Bytes,
203                                                  uint64_t Address,
204                                                  raw_ostream &OS,
205                                                  raw_ostream &CS) const {
206   CommentStream = &CS;
207 
208   Size = 0;
209   // We want to read exactly 4 bytes of data.
210   if (Bytes.size() < 4)
211     return Fail;
212   Size = 4;
213 
214   // Encoded as a small-endian 32-bit word in the stream.
215   uint32_t Insn =
216       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
217 
218   // Calling the auto-generated decoder function.
219   return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
220 }
221 
222 static MCSymbolizer *
createAArch64ExternalSymbolizer(StringRef TT,LLVMOpInfoCallback GetOpInfo,LLVMSymbolLookupCallback SymbolLookUp,void * DisInfo,MCContext * Ctx,std::unique_ptr<MCRelocationInfo> && RelInfo)223 createAArch64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
224                                 LLVMSymbolLookupCallback SymbolLookUp,
225                                 void *DisInfo, MCContext *Ctx,
226                                 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
227   return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo,
228                                              SymbolLookUp, DisInfo);
229 }
230 
LLVMInitializeAArch64Disassembler()231 extern "C" void LLVMInitializeAArch64Disassembler() {
232   TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
233                                          createAArch64Disassembler);
234   TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
235                                          createAArch64Disassembler);
236   TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
237                                        createAArch64ExternalSymbolizer);
238   TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
239                                        createAArch64ExternalSymbolizer);
240 
241   TargetRegistry::RegisterMCDisassembler(TheARM64Target,
242                                          createAArch64Disassembler);
243   TargetRegistry::RegisterMCSymbolizer(TheARM64Target,
244                                        createAArch64ExternalSymbolizer);
245 }
246 
247 static const unsigned FPR128DecoderTable[] = {
248     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
249     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
250     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
251     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
252     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
253     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
254     AArch64::Q30, AArch64::Q31
255 };
256 
DecodeFPR128RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)257 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
258                                               uint64_t Addr,
259                                               const void *Decoder) {
260   if (RegNo > 31)
261     return Fail;
262 
263   unsigned Register = FPR128DecoderTable[RegNo];
264   Inst.addOperand(MCOperand::CreateReg(Register));
265   return Success;
266 }
267 
DecodeFPR128_loRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)268 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
269                                                  uint64_t Addr,
270                                                  const void *Decoder) {
271   if (RegNo > 15)
272     return Fail;
273   return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
274 }
275 
276 static const unsigned FPR64DecoderTable[] = {
277     AArch64::D0,  AArch64::D1,  AArch64::D2,  AArch64::D3,  AArch64::D4,
278     AArch64::D5,  AArch64::D6,  AArch64::D7,  AArch64::D8,  AArch64::D9,
279     AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
280     AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
281     AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
282     AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
283     AArch64::D30, AArch64::D31
284 };
285 
DecodeFPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)286 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
287                                              uint64_t Addr,
288                                              const void *Decoder) {
289   if (RegNo > 31)
290     return Fail;
291 
292   unsigned Register = FPR64DecoderTable[RegNo];
293   Inst.addOperand(MCOperand::CreateReg(Register));
294   return Success;
295 }
296 
297 static const unsigned FPR32DecoderTable[] = {
298     AArch64::S0,  AArch64::S1,  AArch64::S2,  AArch64::S3,  AArch64::S4,
299     AArch64::S5,  AArch64::S6,  AArch64::S7,  AArch64::S8,  AArch64::S9,
300     AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
301     AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
302     AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
303     AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
304     AArch64::S30, AArch64::S31
305 };
306 
DecodeFPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)307 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
308                                              uint64_t Addr,
309                                              const void *Decoder) {
310   if (RegNo > 31)
311     return Fail;
312 
313   unsigned Register = FPR32DecoderTable[RegNo];
314   Inst.addOperand(MCOperand::CreateReg(Register));
315   return Success;
316 }
317 
318 static const unsigned FPR16DecoderTable[] = {
319     AArch64::H0,  AArch64::H1,  AArch64::H2,  AArch64::H3,  AArch64::H4,
320     AArch64::H5,  AArch64::H6,  AArch64::H7,  AArch64::H8,  AArch64::H9,
321     AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
322     AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
323     AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
324     AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
325     AArch64::H30, AArch64::H31
326 };
327 
DecodeFPR16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)328 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
329                                              uint64_t Addr,
330                                              const void *Decoder) {
331   if (RegNo > 31)
332     return Fail;
333 
334   unsigned Register = FPR16DecoderTable[RegNo];
335   Inst.addOperand(MCOperand::CreateReg(Register));
336   return Success;
337 }
338 
339 static const unsigned FPR8DecoderTable[] = {
340     AArch64::B0,  AArch64::B1,  AArch64::B2,  AArch64::B3,  AArch64::B4,
341     AArch64::B5,  AArch64::B6,  AArch64::B7,  AArch64::B8,  AArch64::B9,
342     AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
343     AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
344     AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
345     AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
346     AArch64::B30, AArch64::B31
347 };
348 
DecodeFPR8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)349 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
350                                             uint64_t Addr,
351                                             const void *Decoder) {
352   if (RegNo > 31)
353     return Fail;
354 
355   unsigned Register = FPR8DecoderTable[RegNo];
356   Inst.addOperand(MCOperand::CreateReg(Register));
357   return Success;
358 }
359 
360 static const unsigned GPR64DecoderTable[] = {
361     AArch64::X0,  AArch64::X1,  AArch64::X2,  AArch64::X3,  AArch64::X4,
362     AArch64::X5,  AArch64::X6,  AArch64::X7,  AArch64::X8,  AArch64::X9,
363     AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
364     AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
365     AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
366     AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
367     AArch64::LR,  AArch64::XZR
368 };
369 
DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)370 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
371                                              uint64_t Addr,
372                                              const void *Decoder) {
373   if (RegNo > 31)
374     return Fail;
375 
376   unsigned Register = GPR64DecoderTable[RegNo];
377   Inst.addOperand(MCOperand::CreateReg(Register));
378   return Success;
379 }
380 
DecodeGPR64spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)381 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
382                                                uint64_t Addr,
383                                                const void *Decoder) {
384   if (RegNo > 31)
385     return Fail;
386   unsigned Register = GPR64DecoderTable[RegNo];
387   if (Register == AArch64::XZR)
388     Register = AArch64::SP;
389   Inst.addOperand(MCOperand::CreateReg(Register));
390   return Success;
391 }
392 
393 static const unsigned GPR32DecoderTable[] = {
394     AArch64::W0,  AArch64::W1,  AArch64::W2,  AArch64::W3,  AArch64::W4,
395     AArch64::W5,  AArch64::W6,  AArch64::W7,  AArch64::W8,  AArch64::W9,
396     AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
397     AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
398     AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
399     AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
400     AArch64::W30, AArch64::WZR
401 };
402 
DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)403 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
404                                              uint64_t Addr,
405                                              const void *Decoder) {
406   if (RegNo > 31)
407     return Fail;
408 
409   unsigned Register = GPR32DecoderTable[RegNo];
410   Inst.addOperand(MCOperand::CreateReg(Register));
411   return Success;
412 }
413 
DecodeGPR32spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)414 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
415                                                uint64_t Addr,
416                                                const void *Decoder) {
417   if (RegNo > 31)
418     return Fail;
419 
420   unsigned Register = GPR32DecoderTable[RegNo];
421   if (Register == AArch64::WZR)
422     Register = AArch64::WSP;
423   Inst.addOperand(MCOperand::CreateReg(Register));
424   return Success;
425 }
426 
427 static const unsigned VectorDecoderTable[] = {
428     AArch64::Q0,  AArch64::Q1,  AArch64::Q2,  AArch64::Q3,  AArch64::Q4,
429     AArch64::Q5,  AArch64::Q6,  AArch64::Q7,  AArch64::Q8,  AArch64::Q9,
430     AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
431     AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
432     AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
433     AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
434     AArch64::Q30, AArch64::Q31
435 };
436 
DecodeVectorRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)437 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
438                                               uint64_t Addr,
439                                               const void *Decoder) {
440   if (RegNo > 31)
441     return Fail;
442 
443   unsigned Register = VectorDecoderTable[RegNo];
444   Inst.addOperand(MCOperand::CreateReg(Register));
445   return Success;
446 }
447 
448 static const unsigned QQDecoderTable[] = {
449   AArch64::Q0_Q1,   AArch64::Q1_Q2,   AArch64::Q2_Q3,   AArch64::Q3_Q4,
450   AArch64::Q4_Q5,   AArch64::Q5_Q6,   AArch64::Q6_Q7,   AArch64::Q7_Q8,
451   AArch64::Q8_Q9,   AArch64::Q9_Q10,  AArch64::Q10_Q11, AArch64::Q11_Q12,
452   AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
453   AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
454   AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
455   AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
456   AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
457 };
458 
DecodeQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)459 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
460                                           uint64_t Addr, const void *Decoder) {
461   if (RegNo > 31)
462     return Fail;
463   unsigned Register = QQDecoderTable[RegNo];
464   Inst.addOperand(MCOperand::CreateReg(Register));
465   return Success;
466 }
467 
468 static const unsigned QQQDecoderTable[] = {
469   AArch64::Q0_Q1_Q2,    AArch64::Q1_Q2_Q3,    AArch64::Q2_Q3_Q4,
470   AArch64::Q3_Q4_Q5,    AArch64::Q4_Q5_Q6,    AArch64::Q5_Q6_Q7,
471   AArch64::Q6_Q7_Q8,    AArch64::Q7_Q8_Q9,    AArch64::Q8_Q9_Q10,
472   AArch64::Q9_Q10_Q11,  AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
473   AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
474   AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
475   AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
476   AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
477   AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
478   AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
479   AArch64::Q30_Q31_Q0,  AArch64::Q31_Q0_Q1
480 };
481 
DecodeQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)482 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
483                                            uint64_t Addr, const void *Decoder) {
484   if (RegNo > 31)
485     return Fail;
486   unsigned Register = QQQDecoderTable[RegNo];
487   Inst.addOperand(MCOperand::CreateReg(Register));
488   return Success;
489 }
490 
491 static const unsigned QQQQDecoderTable[] = {
492   AArch64::Q0_Q1_Q2_Q3,     AArch64::Q1_Q2_Q3_Q4,     AArch64::Q2_Q3_Q4_Q5,
493   AArch64::Q3_Q4_Q5_Q6,     AArch64::Q4_Q5_Q6_Q7,     AArch64::Q5_Q6_Q7_Q8,
494   AArch64::Q6_Q7_Q8_Q9,     AArch64::Q7_Q8_Q9_Q10,    AArch64::Q8_Q9_Q10_Q11,
495   AArch64::Q9_Q10_Q11_Q12,  AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
496   AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
497   AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
498   AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
499   AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
500   AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
501   AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
502   AArch64::Q30_Q31_Q0_Q1,   AArch64::Q31_Q0_Q1_Q2
503 };
504 
DecodeQQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)505 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
506                                             uint64_t Addr,
507                                             const void *Decoder) {
508   if (RegNo > 31)
509     return Fail;
510   unsigned Register = QQQQDecoderTable[RegNo];
511   Inst.addOperand(MCOperand::CreateReg(Register));
512   return Success;
513 }
514 
515 static const unsigned DDDecoderTable[] = {
516   AArch64::D0_D1,   AArch64::D1_D2,   AArch64::D2_D3,   AArch64::D3_D4,
517   AArch64::D4_D5,   AArch64::D5_D6,   AArch64::D6_D7,   AArch64::D7_D8,
518   AArch64::D8_D9,   AArch64::D9_D10,  AArch64::D10_D11, AArch64::D11_D12,
519   AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
520   AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
521   AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
522   AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
523   AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
524 };
525 
DecodeDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)526 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
527                                           uint64_t Addr, const void *Decoder) {
528   if (RegNo > 31)
529     return Fail;
530   unsigned Register = DDDecoderTable[RegNo];
531   Inst.addOperand(MCOperand::CreateReg(Register));
532   return Success;
533 }
534 
535 static const unsigned DDDDecoderTable[] = {
536   AArch64::D0_D1_D2,    AArch64::D1_D2_D3,    AArch64::D2_D3_D4,
537   AArch64::D3_D4_D5,    AArch64::D4_D5_D6,    AArch64::D5_D6_D7,
538   AArch64::D6_D7_D8,    AArch64::D7_D8_D9,    AArch64::D8_D9_D10,
539   AArch64::D9_D10_D11,  AArch64::D10_D11_D12, AArch64::D11_D12_D13,
540   AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
541   AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
542   AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
543   AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
544   AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
545   AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
546   AArch64::D30_D31_D0,  AArch64::D31_D0_D1
547 };
548 
DecodeDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)549 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
550                                            uint64_t Addr, const void *Decoder) {
551   if (RegNo > 31)
552     return Fail;
553   unsigned Register = DDDDecoderTable[RegNo];
554   Inst.addOperand(MCOperand::CreateReg(Register));
555   return Success;
556 }
557 
558 static const unsigned DDDDDecoderTable[] = {
559   AArch64::D0_D1_D2_D3,     AArch64::D1_D2_D3_D4,     AArch64::D2_D3_D4_D5,
560   AArch64::D3_D4_D5_D6,     AArch64::D4_D5_D6_D7,     AArch64::D5_D6_D7_D8,
561   AArch64::D6_D7_D8_D9,     AArch64::D7_D8_D9_D10,    AArch64::D8_D9_D10_D11,
562   AArch64::D9_D10_D11_D12,  AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
563   AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
564   AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
565   AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
566   AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
567   AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
568   AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
569   AArch64::D30_D31_D0_D1,   AArch64::D31_D0_D1_D2
570 };
571 
DecodeDDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)572 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
573                                             uint64_t Addr,
574                                             const void *Decoder) {
575   if (RegNo > 31)
576     return Fail;
577   unsigned Register = DDDDDecoderTable[RegNo];
578   Inst.addOperand(MCOperand::CreateReg(Register));
579   return Success;
580 }
581 
DecodeFixedPointScaleImm32(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)582 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
583                                                uint64_t Addr,
584                                                const void *Decoder) {
585   // scale{5} is asserted as 1 in tblgen.
586   Imm |= 0x20;
587   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
588   return Success;
589 }
590 
DecodeFixedPointScaleImm64(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)591 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
592                                                uint64_t Addr,
593                                                const void *Decoder) {
594   Inst.addOperand(MCOperand::CreateImm(64 - Imm));
595   return Success;
596 }
597 
DecodePCRelLabel19(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)598 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
599                                        uint64_t Addr, const void *Decoder) {
600   int64_t ImmVal = Imm;
601   const AArch64Disassembler *Dis =
602       static_cast<const AArch64Disassembler *>(Decoder);
603 
604   // Sign-extend 19-bit immediate.
605   if (ImmVal & (1 << (19 - 1)))
606     ImmVal |= ~((1LL << 19) - 1);
607 
608   if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal *  4, Addr,
609                                      Inst.getOpcode() != AArch64::LDRXl, 0, 4))
610     Inst.addOperand(MCOperand::CreateImm(ImmVal));
611   return Success;
612 }
613 
DecodeMemExtend(llvm::MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)614 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
615                                     uint64_t Address, const void *Decoder) {
616   Inst.addOperand(MCOperand::CreateImm((Imm  >> 1) & 1));
617   Inst.addOperand(MCOperand::CreateImm(Imm & 1));
618   return Success;
619 }
620 
DecodeMRSSystemRegister(llvm::MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)621 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
622                                             uint64_t Address,
623                                             const void *Decoder) {
624   Inst.addOperand(MCOperand::CreateImm(Imm));
625 
626   // Every system register in the encoding space is valid with the syntax
627   // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
628   return Success;
629 }
630 
DecodeMSRSystemRegister(llvm::MCInst & Inst,unsigned Imm,uint64_t Address,const void * Decoder)631 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
632                                             uint64_t Address,
633                                             const void *Decoder) {
634   Inst.addOperand(MCOperand::CreateImm(Imm));
635 
636   return Success;
637 }
638 
DecodeFMOVLaneInstruction(llvm::MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)639 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
640                                               uint64_t Address,
641                                               const void *Decoder) {
642   // This decoder exists to add the dummy Lane operand to the MCInst, which must
643   // be 1 in assembly but has no other real manifestation.
644   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
645   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
646   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
647 
648   if (IsToVec) {
649     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
650     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
651   } else {
652     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
653     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
654   }
655 
656   // Add the lane
657   Inst.addOperand(MCOperand::CreateImm(1));
658 
659   return Success;
660 }
661 
DecodeVecShiftRImm(llvm::MCInst & Inst,unsigned Imm,unsigned Add)662 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
663                                        unsigned Add) {
664   Inst.addOperand(MCOperand::CreateImm(Add - Imm));
665   return Success;
666 }
667 
DecodeVecShiftLImm(llvm::MCInst & Inst,unsigned Imm,unsigned Add)668 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
669                                        unsigned Add) {
670   Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
671   return Success;
672 }
673 
DecodeVecShiftR64Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)674 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
675                                          uint64_t Addr, const void *Decoder) {
676   return DecodeVecShiftRImm(Inst, Imm, 64);
677 }
678 
DecodeVecShiftR64ImmNarrow(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)679 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
680                                                uint64_t Addr,
681                                                const void *Decoder) {
682   return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
683 }
684 
DecodeVecShiftR32Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)685 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
686                                          uint64_t Addr, const void *Decoder) {
687   return DecodeVecShiftRImm(Inst, Imm, 32);
688 }
689 
DecodeVecShiftR32ImmNarrow(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)690 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
691                                                uint64_t Addr,
692                                                const void *Decoder) {
693   return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
694 }
695 
DecodeVecShiftR16Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)696 static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
697                                          uint64_t Addr, const void *Decoder) {
698   return DecodeVecShiftRImm(Inst, Imm, 16);
699 }
700 
DecodeVecShiftR16ImmNarrow(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)701 static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
702                                                uint64_t Addr,
703                                                const void *Decoder) {
704   return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
705 }
706 
DecodeVecShiftR8Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)707 static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
708                                         uint64_t Addr, const void *Decoder) {
709   return DecodeVecShiftRImm(Inst, Imm, 8);
710 }
711 
DecodeVecShiftL64Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)712 static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
713                                          uint64_t Addr, const void *Decoder) {
714   return DecodeVecShiftLImm(Inst, Imm, 64);
715 }
716 
DecodeVecShiftL32Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)717 static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
718                                          uint64_t Addr, const void *Decoder) {
719   return DecodeVecShiftLImm(Inst, Imm, 32);
720 }
721 
DecodeVecShiftL16Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)722 static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
723                                          uint64_t Addr, const void *Decoder) {
724   return DecodeVecShiftLImm(Inst, Imm, 16);
725 }
726 
DecodeVecShiftL8Imm(llvm::MCInst & Inst,unsigned Imm,uint64_t Addr,const void * Decoder)727 static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
728                                         uint64_t Addr, const void *Decoder) {
729   return DecodeVecShiftLImm(Inst, Imm, 8);
730 }
731 
DecodeThreeAddrSRegInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)732 static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
733                                                    uint32_t insn, uint64_t Addr,
734                                                    const void *Decoder) {
735   unsigned Rd = fieldFromInstruction(insn, 0, 5);
736   unsigned Rn = fieldFromInstruction(insn, 5, 5);
737   unsigned Rm = fieldFromInstruction(insn, 16, 5);
738   unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
739   unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
740   unsigned shift = (shiftHi << 6) | shiftLo;
741   switch (Inst.getOpcode()) {
742   default:
743     return Fail;
744   case AArch64::ADDWrs:
745   case AArch64::ADDSWrs:
746   case AArch64::SUBWrs:
747   case AArch64::SUBSWrs:
748     // if shift == '11' then ReservedValue()
749     if (shiftHi == 0x3)
750       return Fail;
751     // Deliberate fallthrough
752   case AArch64::ANDWrs:
753   case AArch64::ANDSWrs:
754   case AArch64::BICWrs:
755   case AArch64::BICSWrs:
756   case AArch64::ORRWrs:
757   case AArch64::ORNWrs:
758   case AArch64::EORWrs:
759   case AArch64::EONWrs: {
760     // if sf == '0' and imm6<5> == '1' then ReservedValue()
761     if (shiftLo >> 5 == 1)
762       return Fail;
763     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
764     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
765     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
766     break;
767   }
768   case AArch64::ADDXrs:
769   case AArch64::ADDSXrs:
770   case AArch64::SUBXrs:
771   case AArch64::SUBSXrs:
772     // if shift == '11' then ReservedValue()
773     if (shiftHi == 0x3)
774       return Fail;
775     // Deliberate fallthrough
776   case AArch64::ANDXrs:
777   case AArch64::ANDSXrs:
778   case AArch64::BICXrs:
779   case AArch64::BICSXrs:
780   case AArch64::ORRXrs:
781   case AArch64::ORNXrs:
782   case AArch64::EORXrs:
783   case AArch64::EONXrs:
784     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
785     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
786     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
787     break;
788   }
789 
790   Inst.addOperand(MCOperand::CreateImm(shift));
791   return Success;
792 }
793 
DecodeMoveImmInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)794 static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
795                                              uint64_t Addr,
796                                              const void *Decoder) {
797   unsigned Rd = fieldFromInstruction(insn, 0, 5);
798   unsigned imm = fieldFromInstruction(insn, 5, 16);
799   unsigned shift = fieldFromInstruction(insn, 21, 2);
800   shift <<= 4;
801   switch (Inst.getOpcode()) {
802   default:
803     return Fail;
804   case AArch64::MOVZWi:
805   case AArch64::MOVNWi:
806   case AArch64::MOVKWi:
807     if (shift & (1U << 5))
808       return Fail;
809     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
810     break;
811   case AArch64::MOVZXi:
812   case AArch64::MOVNXi:
813   case AArch64::MOVKXi:
814     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
815     break;
816   }
817 
818   if (Inst.getOpcode() == AArch64::MOVKWi ||
819       Inst.getOpcode() == AArch64::MOVKXi)
820     Inst.addOperand(Inst.getOperand(0));
821 
822   Inst.addOperand(MCOperand::CreateImm(imm));
823   Inst.addOperand(MCOperand::CreateImm(shift));
824   return Success;
825 }
826 
DecodeUnsignedLdStInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)827 static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
828                                                   uint32_t insn, uint64_t Addr,
829                                                   const void *Decoder) {
830   unsigned Rt = fieldFromInstruction(insn, 0, 5);
831   unsigned Rn = fieldFromInstruction(insn, 5, 5);
832   unsigned offset = fieldFromInstruction(insn, 10, 12);
833   const AArch64Disassembler *Dis =
834       static_cast<const AArch64Disassembler *>(Decoder);
835 
836   switch (Inst.getOpcode()) {
837   default:
838     return Fail;
839   case AArch64::PRFMui:
840     // Rt is an immediate in prefetch.
841     Inst.addOperand(MCOperand::CreateImm(Rt));
842     break;
843   case AArch64::STRBBui:
844   case AArch64::LDRBBui:
845   case AArch64::LDRSBWui:
846   case AArch64::STRHHui:
847   case AArch64::LDRHHui:
848   case AArch64::LDRSHWui:
849   case AArch64::STRWui:
850   case AArch64::LDRWui:
851     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
852     break;
853   case AArch64::LDRSBXui:
854   case AArch64::LDRSHXui:
855   case AArch64::LDRSWui:
856   case AArch64::STRXui:
857   case AArch64::LDRXui:
858     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
859     break;
860   case AArch64::LDRQui:
861   case AArch64::STRQui:
862     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
863     break;
864   case AArch64::LDRDui:
865   case AArch64::STRDui:
866     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
867     break;
868   case AArch64::LDRSui:
869   case AArch64::STRSui:
870     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
871     break;
872   case AArch64::LDRHui:
873   case AArch64::STRHui:
874     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
875     break;
876   case AArch64::LDRBui:
877   case AArch64::STRBui:
878     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
879     break;
880   }
881 
882   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
883   if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
884     Inst.addOperand(MCOperand::CreateImm(offset));
885   return Success;
886 }
887 
DecodeSignedLdStInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)888 static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
889                                                 uint32_t insn, uint64_t Addr,
890                                                 const void *Decoder) {
891   unsigned Rt = fieldFromInstruction(insn, 0, 5);
892   unsigned Rn = fieldFromInstruction(insn, 5, 5);
893   int64_t offset = fieldFromInstruction(insn, 12, 9);
894 
895   // offset is a 9-bit signed immediate, so sign extend it to
896   // fill the unsigned.
897   if (offset & (1 << (9 - 1)))
898     offset |= ~((1LL << 9) - 1);
899 
900   // First operand is always the writeback to the address register, if needed.
901   switch (Inst.getOpcode()) {
902   default:
903     break;
904   case AArch64::LDRSBWpre:
905   case AArch64::LDRSHWpre:
906   case AArch64::STRBBpre:
907   case AArch64::LDRBBpre:
908   case AArch64::STRHHpre:
909   case AArch64::LDRHHpre:
910   case AArch64::STRWpre:
911   case AArch64::LDRWpre:
912   case AArch64::LDRSBWpost:
913   case AArch64::LDRSHWpost:
914   case AArch64::STRBBpost:
915   case AArch64::LDRBBpost:
916   case AArch64::STRHHpost:
917   case AArch64::LDRHHpost:
918   case AArch64::STRWpost:
919   case AArch64::LDRWpost:
920   case AArch64::LDRSBXpre:
921   case AArch64::LDRSHXpre:
922   case AArch64::STRXpre:
923   case AArch64::LDRSWpre:
924   case AArch64::LDRXpre:
925   case AArch64::LDRSBXpost:
926   case AArch64::LDRSHXpost:
927   case AArch64::STRXpost:
928   case AArch64::LDRSWpost:
929   case AArch64::LDRXpost:
930   case AArch64::LDRQpre:
931   case AArch64::STRQpre:
932   case AArch64::LDRQpost:
933   case AArch64::STRQpost:
934   case AArch64::LDRDpre:
935   case AArch64::STRDpre:
936   case AArch64::LDRDpost:
937   case AArch64::STRDpost:
938   case AArch64::LDRSpre:
939   case AArch64::STRSpre:
940   case AArch64::LDRSpost:
941   case AArch64::STRSpost:
942   case AArch64::LDRHpre:
943   case AArch64::STRHpre:
944   case AArch64::LDRHpost:
945   case AArch64::STRHpost:
946   case AArch64::LDRBpre:
947   case AArch64::STRBpre:
948   case AArch64::LDRBpost:
949   case AArch64::STRBpost:
950     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
951     break;
952   }
953 
954   switch (Inst.getOpcode()) {
955   default:
956     return Fail;
957   case AArch64::PRFUMi:
958     // Rt is an immediate in prefetch.
959     Inst.addOperand(MCOperand::CreateImm(Rt));
960     break;
961   case AArch64::STURBBi:
962   case AArch64::LDURBBi:
963   case AArch64::LDURSBWi:
964   case AArch64::STURHHi:
965   case AArch64::LDURHHi:
966   case AArch64::LDURSHWi:
967   case AArch64::STURWi:
968   case AArch64::LDURWi:
969   case AArch64::LDTRSBWi:
970   case AArch64::LDTRSHWi:
971   case AArch64::STTRWi:
972   case AArch64::LDTRWi:
973   case AArch64::STTRHi:
974   case AArch64::LDTRHi:
975   case AArch64::LDTRBi:
976   case AArch64::STTRBi:
977   case AArch64::LDRSBWpre:
978   case AArch64::LDRSHWpre:
979   case AArch64::STRBBpre:
980   case AArch64::LDRBBpre:
981   case AArch64::STRHHpre:
982   case AArch64::LDRHHpre:
983   case AArch64::STRWpre:
984   case AArch64::LDRWpre:
985   case AArch64::LDRSBWpost:
986   case AArch64::LDRSHWpost:
987   case AArch64::STRBBpost:
988   case AArch64::LDRBBpost:
989   case AArch64::STRHHpost:
990   case AArch64::LDRHHpost:
991   case AArch64::STRWpost:
992   case AArch64::LDRWpost:
993     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
994     break;
995   case AArch64::LDURSBXi:
996   case AArch64::LDURSHXi:
997   case AArch64::LDURSWi:
998   case AArch64::STURXi:
999   case AArch64::LDURXi:
1000   case AArch64::LDTRSBXi:
1001   case AArch64::LDTRSHXi:
1002   case AArch64::LDTRSWi:
1003   case AArch64::STTRXi:
1004   case AArch64::LDTRXi:
1005   case AArch64::LDRSBXpre:
1006   case AArch64::LDRSHXpre:
1007   case AArch64::STRXpre:
1008   case AArch64::LDRSWpre:
1009   case AArch64::LDRXpre:
1010   case AArch64::LDRSBXpost:
1011   case AArch64::LDRSHXpost:
1012   case AArch64::STRXpost:
1013   case AArch64::LDRSWpost:
1014   case AArch64::LDRXpost:
1015     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1016     break;
1017   case AArch64::LDURQi:
1018   case AArch64::STURQi:
1019   case AArch64::LDRQpre:
1020   case AArch64::STRQpre:
1021   case AArch64::LDRQpost:
1022   case AArch64::STRQpost:
1023     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1024     break;
1025   case AArch64::LDURDi:
1026   case AArch64::STURDi:
1027   case AArch64::LDRDpre:
1028   case AArch64::STRDpre:
1029   case AArch64::LDRDpost:
1030   case AArch64::STRDpost:
1031     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1032     break;
1033   case AArch64::LDURSi:
1034   case AArch64::STURSi:
1035   case AArch64::LDRSpre:
1036   case AArch64::STRSpre:
1037   case AArch64::LDRSpost:
1038   case AArch64::STRSpost:
1039     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1040     break;
1041   case AArch64::LDURHi:
1042   case AArch64::STURHi:
1043   case AArch64::LDRHpre:
1044   case AArch64::STRHpre:
1045   case AArch64::LDRHpost:
1046   case AArch64::STRHpost:
1047     DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1048     break;
1049   case AArch64::LDURBi:
1050   case AArch64::STURBi:
1051   case AArch64::LDRBpre:
1052   case AArch64::STRBpre:
1053   case AArch64::LDRBpost:
1054   case AArch64::STRBpost:
1055     DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1056     break;
1057   }
1058 
1059   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1060   Inst.addOperand(MCOperand::CreateImm(offset));
1061 
1062   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1063   bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1064   bool IsFP = fieldFromInstruction(insn, 26, 1);
1065 
1066   // Cannot write back to a transfer register (but xzr != sp).
1067   if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1068     return SoftFail;
1069 
1070   return Success;
1071 }
1072 
DecodeExclusiveLdStInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1073 static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
1074                                                    uint32_t insn, uint64_t Addr,
1075                                                    const void *Decoder) {
1076   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1077   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1078   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1079   unsigned Rs = fieldFromInstruction(insn, 16, 5);
1080 
1081   unsigned Opcode = Inst.getOpcode();
1082   switch (Opcode) {
1083   default:
1084     return Fail;
1085   case AArch64::STLXRW:
1086   case AArch64::STLXRB:
1087   case AArch64::STLXRH:
1088   case AArch64::STXRW:
1089   case AArch64::STXRB:
1090   case AArch64::STXRH:
1091     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1092   // FALLTHROUGH
1093   case AArch64::LDARW:
1094   case AArch64::LDARB:
1095   case AArch64::LDARH:
1096   case AArch64::LDAXRW:
1097   case AArch64::LDAXRB:
1098   case AArch64::LDAXRH:
1099   case AArch64::LDXRW:
1100   case AArch64::LDXRB:
1101   case AArch64::LDXRH:
1102   case AArch64::STLRW:
1103   case AArch64::STLRB:
1104   case AArch64::STLRH:
1105   case AArch64::STLLRW:
1106   case AArch64::STLLRB:
1107   case AArch64::STLLRH:
1108   case AArch64::LDLARW:
1109   case AArch64::LDLARB:
1110   case AArch64::LDLARH:
1111     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1112     break;
1113   case AArch64::STLXRX:
1114   case AArch64::STXRX:
1115     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1116   // FALLTHROUGH
1117   case AArch64::LDARX:
1118   case AArch64::LDAXRX:
1119   case AArch64::LDXRX:
1120   case AArch64::STLRX:
1121   case AArch64::LDLARX:
1122   case AArch64::STLLRX:
1123     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1124     break;
1125   case AArch64::STLXPW:
1126   case AArch64::STXPW:
1127     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1128   // FALLTHROUGH
1129   case AArch64::LDAXPW:
1130   case AArch64::LDXPW:
1131     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1132     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1133     break;
1134   case AArch64::STLXPX:
1135   case AArch64::STXPX:
1136     DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1137   // FALLTHROUGH
1138   case AArch64::LDAXPX:
1139   case AArch64::LDXPX:
1140     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1141     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1142     break;
1143   }
1144 
1145   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1146 
1147   // You shouldn't load to the same register twice in an instruction...
1148   if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1149        Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1150       Rt == Rt2)
1151     return SoftFail;
1152 
1153   return Success;
1154 }
1155 
DecodePairLdStInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1156 static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1157                                               uint64_t Addr,
1158                                               const void *Decoder) {
1159   unsigned Rt = fieldFromInstruction(insn, 0, 5);
1160   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1161   unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1162   int64_t offset = fieldFromInstruction(insn, 15, 7);
1163   bool IsLoad = fieldFromInstruction(insn, 22, 1);
1164 
1165   // offset is a 7-bit signed immediate, so sign extend it to
1166   // fill the unsigned.
1167   if (offset & (1 << (7 - 1)))
1168     offset |= ~((1LL << 7) - 1);
1169 
1170   unsigned Opcode = Inst.getOpcode();
1171   bool NeedsDisjointWritebackTransfer = false;
1172 
1173   // First operand is always writeback of base register.
1174   switch (Opcode) {
1175   default:
1176     break;
1177   case AArch64::LDPXpost:
1178   case AArch64::STPXpost:
1179   case AArch64::LDPSWpost:
1180   case AArch64::LDPXpre:
1181   case AArch64::STPXpre:
1182   case AArch64::LDPSWpre:
1183   case AArch64::LDPWpost:
1184   case AArch64::STPWpost:
1185   case AArch64::LDPWpre:
1186   case AArch64::STPWpre:
1187   case AArch64::LDPQpost:
1188   case AArch64::STPQpost:
1189   case AArch64::LDPQpre:
1190   case AArch64::STPQpre:
1191   case AArch64::LDPDpost:
1192   case AArch64::STPDpost:
1193   case AArch64::LDPDpre:
1194   case AArch64::STPDpre:
1195   case AArch64::LDPSpost:
1196   case AArch64::STPSpost:
1197   case AArch64::LDPSpre:
1198   case AArch64::STPSpre:
1199     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1200     break;
1201   }
1202 
1203   switch (Opcode) {
1204   default:
1205     return Fail;
1206   case AArch64::LDPXpost:
1207   case AArch64::STPXpost:
1208   case AArch64::LDPSWpost:
1209   case AArch64::LDPXpre:
1210   case AArch64::STPXpre:
1211   case AArch64::LDPSWpre:
1212     NeedsDisjointWritebackTransfer = true;
1213     // Fallthrough
1214   case AArch64::LDNPXi:
1215   case AArch64::STNPXi:
1216   case AArch64::LDPXi:
1217   case AArch64::STPXi:
1218   case AArch64::LDPSWi:
1219     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1220     DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1221     break;
1222   case AArch64::LDPWpost:
1223   case AArch64::STPWpost:
1224   case AArch64::LDPWpre:
1225   case AArch64::STPWpre:
1226     NeedsDisjointWritebackTransfer = true;
1227     // Fallthrough
1228   case AArch64::LDNPWi:
1229   case AArch64::STNPWi:
1230   case AArch64::LDPWi:
1231   case AArch64::STPWi:
1232     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1233     DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1234     break;
1235   case AArch64::LDNPQi:
1236   case AArch64::STNPQi:
1237   case AArch64::LDPQpost:
1238   case AArch64::STPQpost:
1239   case AArch64::LDPQi:
1240   case AArch64::STPQi:
1241   case AArch64::LDPQpre:
1242   case AArch64::STPQpre:
1243     DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1244     DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1245     break;
1246   case AArch64::LDNPDi:
1247   case AArch64::STNPDi:
1248   case AArch64::LDPDpost:
1249   case AArch64::STPDpost:
1250   case AArch64::LDPDi:
1251   case AArch64::STPDi:
1252   case AArch64::LDPDpre:
1253   case AArch64::STPDpre:
1254     DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1255     DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1256     break;
1257   case AArch64::LDNPSi:
1258   case AArch64::STNPSi:
1259   case AArch64::LDPSpost:
1260   case AArch64::STPSpost:
1261   case AArch64::LDPSi:
1262   case AArch64::STPSi:
1263   case AArch64::LDPSpre:
1264   case AArch64::STPSpre:
1265     DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1266     DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1267     break;
1268   }
1269 
1270   DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1271   Inst.addOperand(MCOperand::CreateImm(offset));
1272 
1273   // You shouldn't load to the same register twice in an instruction...
1274   if (IsLoad && Rt == Rt2)
1275     return SoftFail;
1276 
1277   // ... or do any operation that writes-back to a transfer register. But note
1278   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1279   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1280     return SoftFail;
1281 
1282   return Success;
1283 }
1284 
DecodeAddSubERegInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1285 static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1286                                                 uint32_t insn, uint64_t Addr,
1287                                                 const void *Decoder) {
1288   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1289   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1290   unsigned Rm = fieldFromInstruction(insn, 16, 5);
1291   unsigned extend = fieldFromInstruction(insn, 10, 6);
1292 
1293   unsigned shift = extend & 0x7;
1294   if (shift > 4)
1295     return Fail;
1296 
1297   switch (Inst.getOpcode()) {
1298   default:
1299     return Fail;
1300   case AArch64::ADDWrx:
1301   case AArch64::SUBWrx:
1302     DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1303     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1304     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1305     break;
1306   case AArch64::ADDSWrx:
1307   case AArch64::SUBSWrx:
1308     DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1309     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1310     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1311     break;
1312   case AArch64::ADDXrx:
1313   case AArch64::SUBXrx:
1314     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1315     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1316     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1317     break;
1318   case AArch64::ADDSXrx:
1319   case AArch64::SUBSXrx:
1320     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1321     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1322     DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1323     break;
1324   case AArch64::ADDXrx64:
1325   case AArch64::SUBXrx64:
1326     DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1327     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1328     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1329     break;
1330   case AArch64::SUBSXrx64:
1331   case AArch64::ADDSXrx64:
1332     DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1333     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1334     DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1335     break;
1336   }
1337 
1338   Inst.addOperand(MCOperand::CreateImm(extend));
1339   return Success;
1340 }
1341 
DecodeLogicalImmInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1342 static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1343                                                 uint32_t insn, uint64_t Addr,
1344                                                 const void *Decoder) {
1345   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1346   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1347   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1348   unsigned imm;
1349 
1350   if (Datasize) {
1351     if (Inst.getOpcode() == AArch64::ANDSXri)
1352       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1353     else
1354       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1355     DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1356     imm = fieldFromInstruction(insn, 10, 13);
1357     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1358       return Fail;
1359   } else {
1360     if (Inst.getOpcode() == AArch64::ANDSWri)
1361       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1362     else
1363       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1364     DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1365     imm = fieldFromInstruction(insn, 10, 12);
1366     if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1367       return Fail;
1368   }
1369   Inst.addOperand(MCOperand::CreateImm(imm));
1370   return Success;
1371 }
1372 
DecodeModImmInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1373 static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1374                                             uint64_t Addr,
1375                                             const void *Decoder) {
1376   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1377   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1378   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1379   imm |= fieldFromInstruction(insn, 5, 5);
1380 
1381   if (Inst.getOpcode() == AArch64::MOVID)
1382     DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1383   else
1384     DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1385 
1386   Inst.addOperand(MCOperand::CreateImm(imm));
1387 
1388   switch (Inst.getOpcode()) {
1389   default:
1390     break;
1391   case AArch64::MOVIv4i16:
1392   case AArch64::MOVIv8i16:
1393   case AArch64::MVNIv4i16:
1394   case AArch64::MVNIv8i16:
1395   case AArch64::MOVIv2i32:
1396   case AArch64::MOVIv4i32:
1397   case AArch64::MVNIv2i32:
1398   case AArch64::MVNIv4i32:
1399     Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1400     break;
1401   case AArch64::MOVIv2s_msl:
1402   case AArch64::MOVIv4s_msl:
1403   case AArch64::MVNIv2s_msl:
1404   case AArch64::MVNIv4s_msl:
1405     Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1406     break;
1407   }
1408 
1409   return Success;
1410 }
1411 
DecodeModImmTiedInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1412 static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1413                                                 uint32_t insn, uint64_t Addr,
1414                                                 const void *Decoder) {
1415   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1416   unsigned cmode = fieldFromInstruction(insn, 12, 4);
1417   unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1418   imm |= fieldFromInstruction(insn, 5, 5);
1419 
1420   // Tied operands added twice.
1421   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1422   DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1423 
1424   Inst.addOperand(MCOperand::CreateImm(imm));
1425   Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1426 
1427   return Success;
1428 }
1429 
DecodeAdrInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1430 static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1431                                          uint64_t Addr, const void *Decoder) {
1432   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1433   int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1434   imm |= fieldFromInstruction(insn, 29, 2);
1435   const AArch64Disassembler *Dis =
1436       static_cast<const AArch64Disassembler *>(Decoder);
1437 
1438   // Sign-extend the 21-bit immediate.
1439   if (imm & (1 << (21 - 1)))
1440     imm |= ~((1LL << 21) - 1);
1441 
1442   DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1443   if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1444     Inst.addOperand(MCOperand::CreateImm(imm));
1445 
1446   return Success;
1447 }
1448 
DecodeBaseAddSubImm(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1449 static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1450                                         uint64_t Addr, const void *Decoder) {
1451   unsigned Rd = fieldFromInstruction(insn, 0, 5);
1452   unsigned Rn = fieldFromInstruction(insn, 5, 5);
1453   unsigned Imm = fieldFromInstruction(insn, 10, 14);
1454   unsigned S = fieldFromInstruction(insn, 29, 1);
1455   unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1456 
1457   unsigned ShifterVal = (Imm >> 12) & 3;
1458   unsigned ImmVal = Imm & 0xFFF;
1459   const AArch64Disassembler *Dis =
1460       static_cast<const AArch64Disassembler *>(Decoder);
1461 
1462   if (ShifterVal != 0 && ShifterVal != 1)
1463     return Fail;
1464 
1465   if (Datasize) {
1466     if (Rd == 31 && !S)
1467       DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1468     else
1469       DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1470     DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1471   } else {
1472     if (Rd == 31 && !S)
1473       DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1474     else
1475       DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1476     DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1477   }
1478 
1479   if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1480     Inst.addOperand(MCOperand::CreateImm(ImmVal));
1481   Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1482   return Success;
1483 }
1484 
DecodeUnconditionalBranch(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1485 static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1486                                               uint64_t Addr,
1487                                               const void *Decoder) {
1488   int64_t imm = fieldFromInstruction(insn, 0, 26);
1489   const AArch64Disassembler *Dis =
1490       static_cast<const AArch64Disassembler *>(Decoder);
1491 
1492   // Sign-extend the 26-bit immediate.
1493   if (imm & (1 << (26 - 1)))
1494     imm |= ~((1LL << 26) - 1);
1495 
1496   if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1497     Inst.addOperand(MCOperand::CreateImm(imm));
1498 
1499   return Success;
1500 }
1501 
DecodeSystemPStateInstruction(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1502 static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1503                                                   uint32_t insn, uint64_t Addr,
1504                                                   const void *Decoder) {
1505   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1506   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1507   uint64_t crm = fieldFromInstruction(insn, 8, 4);
1508 
1509   uint64_t pstate_field = (op1 << 3) | op2;
1510 
1511   Inst.addOperand(MCOperand::CreateImm(pstate_field));
1512   Inst.addOperand(MCOperand::CreateImm(crm));
1513 
1514   bool ValidNamed;
1515   const AArch64Disassembler *Dis =
1516       static_cast<const AArch64Disassembler *>(Decoder);
1517   (void)AArch64PState::PStateMapper().toString(pstate_field,
1518       Dis->getSubtargetInfo().getFeatureBits(), ValidNamed);
1519 
1520   return ValidNamed ? Success : Fail;
1521 }
1522 
DecodeTestAndBranch(llvm::MCInst & Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1523 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1524                                         uint64_t Addr, const void *Decoder) {
1525   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1526   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1527   bit |= fieldFromInstruction(insn, 19, 5);
1528   int64_t dst = fieldFromInstruction(insn, 5, 14);
1529   const AArch64Disassembler *Dis =
1530       static_cast<const AArch64Disassembler *>(Decoder);
1531 
1532   // Sign-extend 14-bit immediate.
1533   if (dst & (1 << (14 - 1)))
1534     dst |= ~((1LL << 14) - 1);
1535 
1536   if (fieldFromInstruction(insn, 31, 1) == 0)
1537     DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1538   else
1539     DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1540   Inst.addOperand(MCOperand::CreateImm(bit));
1541   if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1542     Inst.addOperand(MCOperand::CreateImm(dst));
1543 
1544   return Success;
1545 }
1546