| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
373 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 644 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
735 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
797 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1288 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1345 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1376 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1415 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1432 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1451 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1848 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2051 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2075 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2102 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2293 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
2618 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
2889 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2984 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3019 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 618 uint32_t Rd; // the destination register in EmulateADDRdSPImm() local
677 uint32_t Rd; // the destination register in EmulateMOVRdSP() local
740 uint32_t Rd; // the destination register in EmulateMOVRdRm() local
823 uint32_t Rd; // the destination register in EmulateMOVRdImm() local
1063 uint32_t Rd; // the destination register in EmulateMVNImm() local
1125 uint32_t Rd; // the destination register in EmulateMVNReg() local
1821 uint32_t Rd; in EmulateSUBSPImm() local
2582 uint32_t Rd, Rn; in EmulateADDImmARM() local
2642 uint32_t Rd, Rn, Rm; in EmulateADDReg() local
3189 uint32_t Rd; // the destination register in EmulateShiftImm() local
[all …]
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| D | EmulateInstructionARM.h | 260 const uint32_t Rd) in WriteCoreReg()
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP]; in blend_general_float() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1762 static Instr Rd(CPURegister rd) { in Rd() function
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 3684 static Instr Rd(CPURegister rd) { in Rd() function
|