/external/llvm/lib/MC/ |
D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() 72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum()
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 173 unsigned RegNum; member 178 unsigned RegNum; member 1542 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() 1552 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, in CreateVectorList() 1841 unsigned RegNum = isVector ? matchVectorRegName(Name) in matchRegisterNameAlias() local 1867 unsigned RegNum = matchRegisterNameAlias(lowerCase, false); in tryParseRegister() local 1898 unsigned RegNum = matchRegisterNameAlias(Head, true); in tryMatchVectorRegister() local 2948 unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), false); in tryParseGPR64sp0Operand() local 4131 unsigned RegNum = tryParseRegister(); in parseDirectiveReq() local
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/external/llvm/lib/Target/Sparc/AsmParser/ |
D | SparcAsmParser.cpp | 158 unsigned RegNum; member 299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg()
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 465 unsigned RegNum; member 470 unsigned RegNum; member 499 unsigned RegNum; member 1763 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local 2592 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { in CreateCCOut() 2609 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() 2707 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, in CreateVectorList() 2721 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, in CreateVectorListAllLanes() 2733 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, in CreateVectorListIndexed() 2783 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86MCInstLower.cpp | 947 auto GetRegisterName = [](unsigned RegNum) -> StringRef { in getShuffleComment()
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/external/llvm/lib/Target/R600/ |
D | AMDILCFGStructurizer.cpp | 518 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, in insertCondBranchBefore() 529 int NewOpcode, int RegNum) { in insertCondBranchEnd()
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/external/llvm/lib/Target/Mips/ |
D | MipsAsmPrinter.cpp | 266 unsigned RegNum = TRI->getEncodingValue(Reg); in printSavedRegsBitmask() local
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCCodeEmitter.cpp | 1465 unsigned RegNum = GetX86RegNum(MO) << 4; in EncodeInstruction() local
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/external/llvm/lib/Target/Mips/Disassembler/ |
D | MipsDisassembler.cpp | 1760 unsigned RegNum; in DecodeRegListOperand() local 1782 unsigned RegNum = RegLst & 0x3; in DecodeRegListOperand16() local
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/external/clang/include/clang/Basic/ |
D | TargetInfo.h | 668 const unsigned RegNum; member
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXAsmPrinter.cpp | 303 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister() local
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/external/llvm/utils/TableGen/ |
D | CodeGenRegisters.cpp | 1343 unsigned RegNum = Reg.EnumValue; in computeUberSets() local
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/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.cpp | 1120 if (unsigned RegNum = MO2.getReg()) { in printThumbAddrModeRROperand() local
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/external/llvm/lib/Target/ARM/ |
D | ARMLoadStoreOptimizer.cpp | 870 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in MergeLDR_STR() local
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/external/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 2409 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 2395 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local 2423 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
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