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Searched refs:ArmMir2Lir (Results 1 – 7 of 7) sorted by relevance

/art/compiler/dex/quick/arm/
Dtarget_arm.cc72 RegLocation ArmMir2Lir::LocCReturn() { in LocCReturn()
76 RegLocation ArmMir2Lir::LocCReturnRef() { in LocCReturnRef()
80 RegLocation ArmMir2Lir::LocCReturnWide() { in LocCReturnWide()
84 RegLocation ArmMir2Lir::LocCReturnFloat() { in LocCReturnFloat()
88 RegLocation ArmMir2Lir::LocCReturnDouble() { in LocCReturnDouble()
93 RegStorage ArmMir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg()
139 ResourceMask ArmMir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon()
143 constexpr ResourceMask ArmMir2Lir::GetRegMaskArm(RegStorage reg) { in GetRegMaskArm()
150 constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list) { in EncodeArmRegList()
154 constexpr ResourceMask ArmMir2Lir::EncodeArmRegFpcsList(int reg_list) { in EncodeArmRegFpcsList()
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Dutility_arm.cc77 LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { in LoadFPConstantValue()
107 int ArmMir2Lir::ModifiedImmediate(uint32_t value) { in ModifiedImmediate()
134 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { in InexpensiveConstantInt()
138 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { in InexpensiveConstantInt()
203 bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat()
207 bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong()
211 bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { in InexpensiveConstantDouble()
223 LIR* ArmMir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
257 LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
263 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
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Dint_arm.cc35 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
50 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
80 void ArmMir2Lir::UpdateIT(LIR* it, const char* new_guide) { in UpdateIT()
110 void ArmMir2Lir::OpEndIT(LIR* it) { in OpEndIT()
133 void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { in GenCmpLong()
166 void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, in GenFusedLongCmpImmBranch()
217 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
242 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect()
318 void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch()
380 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
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Dcall_arm.cc56 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargeSparseSwitch()
101 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargePackedSwitch()
147 void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { in GenMonitorEnter()
229 void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { in GenMonitorExit()
338 void ArmMir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException()
349 void ArmMir2Lir::UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) { in UnconditionallyMarkGCCard()
367 void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence()
529 void ArmMir2Lir::GenExitSequence() { in GenExitSequence()
583 void ArmMir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence()
587 void ArmMir2Lir::GenSpecialEntryForSuspend() { in GenSpecialEntryForSuspend()
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Dfp_arm.cc26 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat()
72 void ArmMir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
119 void ArmMir2Lir::GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantFloat()
130 void ArmMir2Lir::GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantDouble()
145 void ArmMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) { in GenConversion()
245 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch()
296 void ArmMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP()
354 void ArmMir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat()
362 void ArmMir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { in GenNegDouble()
388 bool ArmMir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat()
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Dassemble_arm.cc82 const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = {
1056 void ArmMir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in ReplaceFixup()
1067 void ArmMir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in InsertFixupBefore()
1085 uint8_t* ArmMir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs()
1240 void ArmMir2Lir::AssembleLIR() { in AssembleLIR()
1636 size_t ArmMir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize()
1642 uint32_t ArmMir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { in LinkFixupInsns()
1676 void ArmMir2Lir::AssignDataOffsets() { in AssignDataOffsets()
Dcodegen_arm.h29 class ArmMir2Lir FINAL : public Mir2Lir {
59 ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);