Searched refs:IsWide (Results 1 – 11 of 11) sorted by relevance
| /art/compiler/dex/quick/ |
| D | ralloc_util.cc | 149 info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(), in DumpRegPool()
348 if (info->IsWide()) { in AllocTempBody()
353 DCHECK(partner->IsWide()); in AllocTempBody()
377 if (info->IsWide()) { in AllocTempBody()
380 DCHECK(partner->IsWide()); in AllocTempBody()
500 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { in AllocLiveReg()
730 DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() && in FlushRegWide()
771 if (info->IsWide()) { in FlushSpecificReg()
869 if (info_lo->IsWide() && info_lo->Partner().NotExactlyEquals(info_hi->GetReg())) { in MarkWide()
872 if (info_hi->IsWide() && info_hi->Partner().NotExactlyEquals(info_lo->GetReg())) { in MarkWide()
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| D | mir_to_lir.cc | 58 i += m2l_->in_to_reg_storage_mapping_.GetShorty(i).IsWide() ? 2u : 1u) { in Compile()
214 (arg.IsWide() && reg_arg.GetWideKind() == kWide) ? k64 : k32; in SpillArg()
226 (arg.IsWide() && reg_arg.GetWideKind() == kWide) ? k64 : k32; in UnspillArg()
288 RegLocation rl_dest = IsWide(size) ? GetReturnWide(ret_reg_class) : GetReturn(ret_reg_class); in GenSpecialIGet()
291 r_result = IsWide(size) ? AllocTypedTempWide(rl_dest.fp, reg_class) in GenSpecialIGet()
301 if (IsWide(size)) { in GenSpecialIGet()
361 RegStorage reg_src = LoadArg(data.src_arg, reg_class, IsWide(size)); in GenSpecialIPut()
1431 if (arg.IsWide()) { in Initialize()
1437 if (arg.IsWide() && !reg.Is64Bit()) { in Initialize()
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| D | mir_to_lir-inl.h | 34 if (p->IsWide()) { in ClobberBody()
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| D | gen_common.cc | 714 if (IsWide(size)) { in GenSput()
801 if (IsWide(size)) { in GenSget()
842 if (IsWide(size)) { in GenSget()
889 if (IsWide(size)) { in GenIGet()
931 if (IsWide(size)) { in GenIGet()
957 if (IsWide(size)) { in GenIPut()
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| D | mir_to_lir.h | 358 bool IsWide() { return wide_value_; } in IsWide() function
1177 static constexpr bool IsWide(OpSize size) { in IsWide() function
1869 bool IsWide() { return type_ == 'J' || type_ == 'D'; } in IsWide() function
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| D | gen_invoke.cc | 1171 RegLocation rl_dest = IsWide(size) ? InlineTargetWide(info) : InlineTarget(info); // result reg in GenInlinedReverseBytes()
1177 …RegLocation rl_i = IsWide(size) ? LoadValueWide(rl_src_i, kCoreReg) : LoadValue(rl_src_i, kCoreReg… in GenInlinedReverseBytes()
1179 if (IsWide(size)) { in GenInlinedReverseBytes()
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| /art/compiler/dex/quick/mips/ |
| D | target_mips.cc | 258 if (arg.IsWide() && cur_core_reg_ < coreArgMappingToPhysicalRegSize) { in GetNextReg()
279 arg.IsWide() ? kWide : kNotWide); in GetNextReg()
283 DCHECK(!(arg.IsWide() && arg.IsRef())); in GetNextReg()
285 arg.IsRef() ? kRef : (arg.IsWide() ? kWide : kNotWide)); in GetNextReg()
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| /art/compiler/dex/quick/arm64/ |
| D | target_arm64.cc | 830 result = arg.IsWide() ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg); in GetNextReg()
839 DCHECK(!(arg.IsWide() && arg.IsRef())); in GetNextReg()
840 result = (arg.IsWide() || arg.IsRef()) ? in GetNextReg()
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| D | int_arm64.cc | 1784 A64Opcode wide = IsWide(size) ? WIDE(0) : UNWIDE(0); in GenInlinedReverseBits()
1786 RegLocation rl_dest = IsWide(size) ? InlineTargetWide(info) : InlineTarget(info); // result reg in GenInlinedReverseBits()
1788 RegLocation rl_i = IsWide(size) ? in GenInlinedReverseBits()
1791 IsWide(size) ? StoreValueWide(rl_dest, rl_result) : StoreValue(rl_dest, rl_result); in GenInlinedReverseBits()
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| /art/compiler/dex/quick/arm/ |
| D | target_arm.cc | 947 if (arg.IsWide()) { in GetNextReg()
966 if (!kArm32QuickCodeUseSoftFloat && arg.IsWide() && cur_core_reg_ == 0) { in GetNextReg()
971 if (arg.IsWide() && cur_core_reg_ < coreArgMappingToPhysicalRegSize) { in GetNextReg()
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| /art/compiler/dex/quick/x86/ |
| D | target_x86.cc | 2372 arg.IsWide() ? kWide : kNotWide); in GetNextReg()
2377 arg.IsRef() ? kRef : (arg.IsWide() ? kWide : kNotWide)); in GetNextReg()
2393 arg.IsWide() ? kWide : kNotWide); in GetNextReg()
2398 if (arg.IsWide()) { in GetNextReg()
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