/art/compiler/dex/quick/mips/ |
D | int_mips.cc | 434 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); in GenMultiplyByTwoBitMultiplier() 447 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); in GenDivZeroCheckWide() 501 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src2.reg.GetLow(), rl_src1.reg.GetLow()); in GenAddLong() 503 OpRegRegReg(kOpAdd, t_reg, rl_src2.reg.GetHigh(), rl_src1.reg.GetHigh()); in GenAddLong() 506 OpRegRegReg(kOpAdd, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenAddLong() 525 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenSubLong() 526 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenSubLong() 527 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenSubLong() 605 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); in GenLongOp() 658 OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); in GenNegLong() [all …]
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D | call_mips.cc | 110 OpRegRegReg(kOpAdd, r_end, r_end, r_base); in GenLargeSparseSwitch() 125 OpRegRegReg(kOpAdd, rs_ra, rs_ra, r_disp); in GenLargeSparseSwitch() 181 OpRegRegReg(kOpSub, r_key, rl_src.reg, r_key); in GenLargePackedSwitch() 206 OpRegRegReg(kOpAdd, rs_ra, rs_ra, r_disp); in GenLargePackedSwitch()
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D | utility_mips.cc | 304 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::MipsMir2Lir 487 return OpRegRegReg(op, r_dest_src1, r_dest_src1, r_src2); in OpRegReg()
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D | codegen_mips.h | 214 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
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/art/compiler/dex/quick/arm/ |
D | int_arm.cc | 143 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenCmpLong() 227 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); in GenSelectConst32() 572 OpRegRegReg(kOpSub, rl_result.reg, rl_src.reg, tmp1); in SmallLiteralDivRem() 748 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); in GenDivRem() 756 OpRegRegReg(kOpDiv, temp, reg1, reg2); in GenDivRem() 758 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); in GenDivRem() 903 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); in GenInlinedCas() 1233 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); in GenNegLong() 1234 OpRegRegReg(kOpSbc, rl_result.reg.GetHigh(), z_reg, t_reg); in GenNegLong() 1237 OpRegRegReg(kOpSub, rl_result.reg.GetLow(), z_reg, rl_src.reg.GetLow()); in GenNegLong() [all …]
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D | call_arm.cc | 171 OpRegRegReg(kOpOr, rs_r2, rs_r2, rs_r1); in GenMonitorEnter() 204 OpRegRegReg(kOpOr, rs_r2, rs_r2, rs_r1); in GenMonitorEnter()
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D | utility_arm.cc | 509 LIR* ArmMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::ArmMir2Lir 781 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index); in LoadBaseIndexed() 848 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index); in StoreBaseIndexed()
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D | codegen_arm.h | 217 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
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/art/compiler/dex/quick/ |
D | gen_common.cc | 1465 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenLong3Addr() 1466 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenLong3Addr() 1470 OpRegRegReg(first_op, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenLong3Addr() 1471 OpRegRegReg(second_op, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenLong3Addr() 1601 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); in GenArithOpInt() 1607 OpRegRegReg(op, rl_result.reg, rl_src1.reg, rl_src2.reg); in GenArithOpInt() 1688 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); in HandleEasyDivRem() 1693 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg); in HandleEasyDivRem() 1701 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg); in HandleEasyDivRem() 1703 OpRegRegReg(kOpSub, rl_result.reg, t_reg2, t_reg1); in HandleEasyDivRem() [all …]
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D | gen_invoke.cc | 960 LIR* or_inst = OpRegRegReg(kOpOr, reg_slow_path, reg_slow_path, reg_disabled); in GenInlinedReferenceGetReferent() 1100 OpRegRegReg(kOpAdc, rl_result.reg, rl_result.reg, t_reg); in GenInlinedStringIsEmptyOrLength() 1218 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); in GenInlinedAbsInt() 1254 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); in GenInlinedAbsLong() 1259 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), sign_reg); in GenInlinedAbsLong() 1260 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), sign_reg); in GenInlinedAbsLong() 1462 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); in GenInlinedUnsafeGet() 1510 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); in GenInlinedUnsafePut()
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D | mir_to_lir.h | 1456 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
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/art/compiler/dex/quick/x86/ |
D | int_x86.cc | 490 OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); in GenFusedLongCmpImmBranch() 1470 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); in GenMultiplyByTwoBitMultiplier() 1488 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); in GenDivZeroCheckWide() 3221 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); in GenArithOpInt() 3260 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt() 3272 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt() 3303 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt() 3310 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); in GenArithOpInt() 3471 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); in GenShiftOpLong()
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D | codegen_x86.h | 313 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
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D | target_x86.cc | 1155 OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); in GenInlinedArrayCopyCharArray() 1180 OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); in GenInlinedArrayCopyCharArray()
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D | utility_x86.cc | 451 LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegReg() function in art::X86Mir2Lir
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/art/compiler/dex/quick/arm64/ |
D | int_arm64.cc | 93 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg)); in GenShiftOpLong() 516 OpRegRegReg(kOpAdd, r_long_mul, rl_src.reg, r_long_mul); in SmallLiteralDivRem64() 642 OpRegRegReg(kOpDiv, rl_result.reg, r_src1, r_src2); in GenDivRem() 655 OpRegRegReg(kOpDiv, temp, r_src1, r_src2); in GenDivRem() 771 OpRegRegReg(kOpAdd, r_ptr, rl_object.reg, rl_offset.reg); in GenInlinedCas()
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D | call_arm64.cc | 182 OpRegRegReg(kOpOr, rs_w1, rs_w1, rs_w3); in GenMonitorEnter()
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D | codegen_arm64.h | 220 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
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D | utility_arm64.cc | 801 LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() function in art::Arm64Mir2Lir
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