Searched refs:PC (Results 1 – 13 of 13) sorted by relevance
/art/runtime/arch/arm/ |
D | registers_arm.cc | 29 if (rhs >= R0 && rhs <= PC) { in operator <<()
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D | context_arm.cc | 32 gprs_[PC] = &pc_; in Reset() 35 pc_ = ArmContext::kBadGprBase + PC; in Reset()
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D | registers_arm.h | 48 PC = 15, enumerator
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D | context_arm.h | 45 SetGPR(PC, new_pc); in SetPC()
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D | quick_entrypoints_arm.S | 447 ldr r2, [r0, #60] @ r2 = r15 (PC from gprs_ 60=4*15)
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/art/compiler/utils/arm/ |
D | assembler_thumb2.cc | 121 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. in tst() 127 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. in teq() 673 EmitDataProcessing(AL, TST, 1, PC, R0, ShifterOperand(0)); in MarkExceptionHandler() 816 case TST: thumb_opcode = 0U /* 0b0000 */; set_cc = true; rd = PC; break; in Emit32BitDataProcessing() 817 case TEQ: thumb_opcode = 4U /* 0b0100 */; set_cc = true; rd = PC; break; in Emit32BitDataProcessing() 818 case CMP: thumb_opcode = 13U /* 0b1101 */; set_cc = true; rd = PC; break; in Emit32BitDataProcessing() 819 case CMN: thumb_opcode = 8U /* 0b1000 */; set_cc = true; rd = PC; break; in Emit32BitDataProcessing() 821 case MOV: thumb_opcode = 2U /* 0b0010 */; rn = PC; break; in Emit32BitDataProcessing() 823 case MVN: thumb_opcode = 3U /* 0b0011 */; rn = PC; break; in Emit32BitDataProcessing() 1374 if (IsHighRegister(rn) && rn != SP && rn != PC) { in EmitLoadStore() [all …]
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D | assembler_arm32.cc | 124 CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. in tst() 130 CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. in teq() 569 EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); in MarkExceptionHandler() 622 if (!ad.IsImmediate() && ad.GetRegisterOffset() == PC) { in EmitMemOp() 735 CHECK_NE(rd, PC); in clz() 736 CHECK_NE(rm, PC); in clz() 877 CHECK_NE(rt, PC); in vmovsr() 892 CHECK_NE(rt, PC); in vmovrs() 909 CHECK_NE(rt, PC); in vmovsrr() 912 CHECK_NE(rt2, PC); in vmovsrr() [all …]
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D | assembler_arm.h | 192 CHECK_NE(rm, PC); in rn_() 198 CHECK_NE(rm, PC); in rn_() 203 rn_(PC), rm_(R0), offset_(offset), in Address()
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D | assembler_arm.cc | 39 if (rhs >= R0 && rhs <= PC) { in operator <<() 444 RegList core_spill_mask = 1 << PC; in RemoveFrame()
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/art/compiler/trampolines/ |
D | trampoline_compiler.cc | 38 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value()); in CreateTrampoline() 42 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value()); in CreateTrampoline() 45 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value()); in CreateTrampoline()
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/art/disassembler/ |
D | disassembler_arm.cc | 1355 if (Rt.r == PC && is_load && !is_word) { in DumpThumb32() 1361 } else if (Rn.r == PC || U != 0u) { in DumpThumb32() 1364 if (Rn.r == PC && is_half) { in DumpThumb32() 1382 bool unpred = (Rt.r == SP && !is_word) || (Rt.r == PC && !is_load); in DumpThumb32() 1383 if (Rn.r == PC && !is_load) { in DumpThumb32() 1386 } else if (Rn.r == PC || U != 0u) { in DumpThumb32() 1393 } else if (Rn.r == PC) { in DumpThumb32() 1408 unpred = unpred || (Rm.rm.r == SP) || (Rm.rm.r == PC); in DumpThumb32()
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/art/compiler/linker/arm/ |
D | relative_patcher_thumb2.cc | 82 arm::kLoadWord, arm::PC, arm::R0, in CompileThunkCode()
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/art/compiler/optimizing/ |
D | code_generator_arm.cc | 48 { R5, R6, R7, R8, R10, R11, PC }; 396 AddAllocatedRegister(Location::RegisterLocation(PC)); in CodeGeneratorARM() 457 blocked_core_registers_[PC] = true; in SetupBlockedRegisters() 543 uint32_t push_mask = (core_spill_mask_ & (~(1 << PC))) | 1 << LR; in GenerateFrameEntry()
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