| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 1484 m2l->cfi().RelOffset(DwarfCoreReg(reg1), offset << reg_log2_size); in SpillCoreRegs()
1488 m2l->cfi().RelOffset(DwarfCoreReg(reg2), offset << reg_log2_size); in SpillCoreRegs()
1489 m2l->cfi().RelOffset(DwarfCoreReg(reg1), (offset + 1) << reg_log2_size); in SpillCoreRegs()
1504 m2l->cfi().RelOffset(DwarfFpReg(reg1), offset << reg_log2_size); in SpillFPRegs()
1508 m2l->cfi().RelOffset(DwarfFpReg(reg2), offset << reg_log2_size); in SpillFPRegs()
1509 m2l->cfi().RelOffset(DwarfFpReg(reg1), (offset + 1) << reg_log2_size); in SpillFPRegs()
1578 m2l->cfi().RelOffset(DwarfFpReg(reg1), kArm64PointerSize); in SpillRegsPreIndexed()
1585 m2l->cfi().RelOffset(DwarfFpReg(reg1), 0); in SpillRegsPreIndexed()
1594 m2l->cfi().RelOffset(DwarfFpReg(reg2), 0); in SpillRegsPreIndexed()
1595 m2l->cfi().RelOffset(DwarfFpReg(reg1), kArm64PointerSize); in SpillRegsPreIndexed()
[all …]
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| D | call_arm64.cc | 438 cfi_.RelOffset(DwarfCoreReg(rxLR), 8); in GenSpecialEntryForSuspend()
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| /art/compiler/dwarf/ |
| D | dwarf_test.cc | 113 opcodes.RelOffset(Reg(0), 0); // push R0 in TEST_F()
115 opcodes.RelOffset(Reg(1), 4); // push R1 in TEST_F()
158 opcodes.RelOffset(Reg::X86_64Core(i), 0); in TEST_F()
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| D | debug_frame_opcode_writer.h | 71 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() function
90 RelOffset(Reg(reg_base.num() + i), offset); in RelOffsetForMany()
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| /art/compiler/dex/quick/x86/ |
| D | call_x86.cc | 305 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rDI.GetRegNum()), 0); in GenSpecialEntryForSuspend()
308 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rSI.GetRegNum()), 0); in GenSpecialEntryForSuspend()
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| D | target_x86.cc | 750 cfi_.RelOffset(DwarfCoreReg(cu_->target64, reg), offset); in SpillCoreRegs()
786 cfi_.RelOffset(DwarfFpReg(cu_->target64, reg), offset); in SpillFPRegs()
1323 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rDI.GetReg()), 0); in GenInlinedIndexOf()
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| D | int_x86.cc | 957 cfi_.RelOffset(DwarfCoreReg(cu_->target64, tmp.GetReg()), 0); in GenInlinedMinMax()
1168 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rDI.GetReg()), 0); in GenInlinedCas()
1178 cfi_.RelOffset(DwarfCoreReg(cu_->target64, rs_rSI.GetReg()), 0); in GenInlinedCas()
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 659 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
660 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters()
666 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
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| /art/compiler/dex/quick/mips/ |
| D | call_mips.cc | 400 cfi_.RelOffset(DwarfCoreReg(rRA), frame_size_ - (cu_->target64 ? 8 : 4)); in GenSpecialEntryForSuspend()
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| D | target_mips.cc | 859 cfi_.RelOffset(DwarfCoreReg(reg), offset); in SpillCoreRegs()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 557 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
562 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 1082 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
1087 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.cc | 2370 cfi_.RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
2387 cfi_.RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 1723 cfi_.RelOffset(DWARFReg(spill), 0); in BuildFrame()
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.cc | 531 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
545 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
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| D | code_generator_mips64.cc | 519 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
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| D | code_generator_x86.cc | 494 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
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