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Searched refs:SP (Results 1 – 25 of 30) sorted by relevance

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/art/compiler/utils/arm64/
Dassembler_arm64.cc58 StoreToOffset(ETR, SP, offset.Int32Value()); in GetCurrentThread()
64 AddConstant(SP, -adjust); in IncreaseFrameSize()
71 AddConstant(SP, adjust); in DecreaseFrameSize()
113 CHECK_NE(source, SP); in StoreToOffset()
131 StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value()); in Store()
134 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in Store()
136 StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value()); in Store()
139 StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value()); in Store()
146 StoreWToOffset(kStoreWord, src.AsOverlappingWRegister(), SP, in StoreRef()
153 StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); in StoreRawPtr()
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Dmanaged_register_arm64_test.cc93 reg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
101 EXPECT_EQ(SP, reg.AsXRegister()); in TEST()
157 xreg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
296 Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromXRegister(SP); in TEST()
379 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
401 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
423 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
444 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); in TEST()
448 EXPECT_NE(SP, reg_o.AsOverlappingXRegister()); in TEST()
461 reg = Arm64ManagedRegister::FromXRegister(SP); in TEST()
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/art/compiler/utils/arm/
Dassembler_arm.cc415 StoreToOffset(kStoreWord, R0, SP, 0); in BuildFrame()
426 StoreToOffset(kStoreWord, reg.AsCoreRegister(), SP, offset); in BuildFrame()
429 StoreSToOffset(reg.AsSRegister(), SP, offset); in BuildFrame()
432 StoreDToOffset(reg.AsDRegister(), SP, offset); in BuildFrame()
474 AddConstant(SP, -adjust); in IncreaseFrameSize()
479 AddConstant(SP, adjust); in DecreaseFrameSize()
489 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); in Store()
492 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); in Store()
494 SP, dest.Int32Value() + 4); in Store()
496 StoreSToOffset(src.AsSRegister(), SP, dest.Int32Value()); in Store()
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Dassembler_thumb2_test.cc255 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F()
256 __ StoreToOffset(type, arm::IP, arm::SP, offset); in TEST_F()
271 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F()
272 __ StoreToOffset(type, arm::IP, arm::SP, offset); in TEST_F()
299 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F()
308 __ StoreToOffset(type, arm::R11, arm::SP, offset); in TEST_F()
323 __ StoreToOffset(type, arm::R0, arm::SP, offset); in TEST_F()
327 __ StoreToOffset(type, arm::R11, arm::SP, offset); in TEST_F()
Dassembler_thumb2.cc705 if ((opcode == ADD || opcode == SUB) && rn == SP && so.IsImmediate()) { in Is32BitDataProcessing()
707 if (rd == SP) { in Is32BitDataProcessing()
1092 if (rd == SP && rn == SP) { in Emit16BitAddSub()
1106 } else if (rd != SP && rn == SP) { in Emit16BitAddSub()
1143 if (rd == SP && rn == SP) { in Emit16BitAddSub()
1374 if (IsHighRegister(rn) && rn != SP && rn != PC) { in EmitLoadStore()
1387 if (rn == SP && offset >= (1 << 10)) { in EmitLoadStore()
1426 if (rn == SP) { in EmitLoadStore()
1531 if (!must_be_32bit && base == SP && bam == (load ? IA_W : DB_W) && in EmitMultiMemOp()
1570 CHECK_EQ((regs & (1 << SP)), 0); in EmitMultiMemOp()
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Dassembler_arm32.cc876 CHECK_NE(rt, SP); in vmovsr()
891 CHECK_NE(rt, SP); in vmovrs()
908 CHECK_NE(rt, SP); in vmovsrr()
911 CHECK_NE(rt2, SP); in vmovsrr()
929 CHECK_NE(rt, SP); in vmovrrs()
932 CHECK_NE(rt2, SP); in vmovrrs()
950 CHECK_NE(rt, SP); in vmovdrr()
953 CHECK_NE(rt2, SP); in vmovdrr()
970 CHECK_NE(rt, SP); in vmovrrd()
973 CHECK_NE(rt2, SP); in vmovrrd()
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/art/compiler/utils/mips/
Dassembler_mips.cc556 StoreToOffset(kStoreWord, RA, SP, stack_offset); in BuildFrame()
561 StoreToOffset(kStoreWord, reg, SP, stack_offset); in BuildFrame()
566 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0); in BuildFrame()
571 StoreToOffset(kStoreWord, reg, SP, frame_size + kFramePointerSize + (i * kFramePointerSize)); in BuildFrame()
584 LoadFromOffset(kLoadWord, reg, SP, stack_offset); in RemoveFrame()
588 LoadFromOffset(kLoadWord, RA, SP, stack_offset); in RemoveFrame()
604 AddConstant(SP, SP, -adjust); in IncreaseFrameSize()
610 AddConstant(SP, SP, adjust); in DecreaseFrameSize()
620 StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); in Store()
623 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); in Store()
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/art/compiler/utils/mips64/
Dassembler_mips64.cc1081 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); in BuildFrame()
1086 StoreToOffset(kStoreDoubleword, reg, SP, stack_offset); in BuildFrame()
1091 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0); in BuildFrame()
1104 reg.AsFpuRegister(), SP, offset); in BuildFrame()
1108 reg.AsGpuRegister(), SP, offset); in BuildFrame()
1123 LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset); in RemoveFrame()
1127 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); in RemoveFrame()
1143 Daddiu64(SP, SP, static_cast<int32_t>(-adjust)); in IncreaseFrameSize()
1149 Daddiu64(SP, SP, static_cast<int32_t>(adjust)); in DecreaseFrameSize()
1160 StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); in Store()
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/art/runtime/arch/arm64/
Dcontext_arm64.cc33 gprs_[SP] = &sp_; in Reset()
36 sp_ = Arm64Context::kBadGprBase + SP; in Reset()
130 DCHECK_EQ(SP, 31); in DoLongJump()
Dcontext_arm64.h41 SetGPR(SP, new_sp); in SetSP()
Dregisters_arm64.h58 SP = 31, // SP and XZR are encoded in instructions using the register enumerator
/art/runtime/arch/mips/
Dcontext_mips.cc31 gprs_[SP] = &sp_; in Reset()
34 sp_ = MipsContext::kBadGprBase + SP; in Reset()
Dregisters_mips.h59 SP = 29, // Stack pointer. enumerator
Dcontext_mips.h40 SetGPR(SP, new_sp); in SetSP()
/art/compiler/optimizing/
Dcode_generator_arm.cc358 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index); in SaveCoreRegister()
363 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index); in RestoreCoreRegister()
368 __ StoreSToOffset(static_cast<SRegister>(reg_id), SP, stack_index); in SaveFloatingPointRegister()
373 __ LoadSFromOffset(static_cast<SRegister>(reg_id), SP, stack_index); in RestoreFloatingPointRegister()
455 blocked_core_registers_[SP] = true; in SetupBlockedRegisters()
536 __ AddConstant(IP, SP, -static_cast<int32_t>(GetStackOverflowReservedBytes(kArm))); in GenerateFrameEntry()
554 __ AddConstant(SP, -adjust); in GenerateFrameEntry()
556 __ StoreToOffset(kStoreWord, R0, SP, 0); in GenerateFrameEntry()
566 __ AddConstant(SP, adjust); in GenerateFrameExit()
721 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex()); in Move32()
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Dcommon_arm64.h31 static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32),
35 if (code == SP) { in VIXLRegCodeFromART()
46 return SP; in ARTRegCodeFromVIXL()
Dcode_generator_mips64.cc440 __ Ld(GpuRegister(reg), SP, 0); in RestoreScratch()
447 __ Sd(GpuRegister(reg), SP, 0); in SpillScratch()
461 SP, in Exchange()
465 SP, in Exchange()
469 SP, in Exchange()
471 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset); in Exchange()
488 SP, in GenerateFrameEntry()
518 __ Sd(reg, SP, ofs); in GenerateFrameEntry()
527 __ Sdc1(reg, SP, ofs); in GenerateFrameEntry()
539 __ Sd(kMethodRegisterArgument, SP, kCurrentMethodStackOffset); in GenerateFrameEntry()
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/art/runtime/arch/arm/
Dcontext_arm.cc31 gprs_[SP] = &sp_; in Reset()
34 sp_ = ArmContext::kBadGprBase + SP; in Reset()
Dregisters_arm.h46 SP = 13, enumerator
Dcontext_arm.h41 SetGPR(SP, new_sp); in SetSP()
Dquick_entrypoints_arm.S336 str r12, [sp, #-16]! @ expand the frame and pass SP
338 bl \cxx_name @ (method_idx, this, caller, Thread*, SP)
908 mov r3, sp @ pass SP
909 blx artQuickResolutionTrampoline @ (Method* called, receiver, Thread*, SP)
1013 mov r2, sp @ pass SP
1014 blx artQuickToInterpreterBridge @ (Method* method, Thread*, SP)
1064 mov r1, r12 @ pass SP
1065 blx artInstrumentationMethodExitFromCode @ (Thread*, SP, gpr_res, fpr_res)
/art/runtime/arch/mips64/
Dcontext_mips64.cc31 gprs_[SP] = &sp_; in Reset()
34 sp_ = Mips64Context::kBadGprBase + SP; in Reset()
Dregisters_mips64.h59 SP = 29, // Stack pointer. enumerator
Dcontext_mips64.h40 SetGPR(SP, new_sp); in SetSP()
/art/compiler/utils/
Dassembler_thumb_test.cc371 __ ldr(R3, Address(SP, 24)); in TEST()
396 __ str(R3, Address(SP, 24)); in TEST()
777 __ add(R2, SP, ShifterOperand(0x50)); // 16 bit. in TEST()
778 __ add(SP, SP, ShifterOperand(0x50)); // 16 bit. in TEST()
779 __ add(R8, SP, ShifterOperand(0x50)); // 32 bit. in TEST()
781 __ add(R2, SP, ShifterOperand(0xf00)); // 32 bit due to imm size. in TEST()
782 __ add(SP, SP, ShifterOperand(0xf00)); // 32 bit due to imm size. in TEST()
784 __ sub(SP, SP, ShifterOperand(0x50)); // 16 bit in TEST()
785 __ sub(R0, SP, ShifterOperand(0x50)); // 32 bit in TEST()
786 __ sub(R8, SP, ShifterOperand(0x50)); // 32 bit. in TEST()
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