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Searched refs:X86Mir2Lir (Results 1 – 8 of 8) sorted by relevance

/art/compiler/dex/quick/x86/
Dquick_assemble_x86_test.cc32 X86Mir2Lir* Prepare(InstructionSet target) { in Prepare()
96 X86Mir2Lir* m2l = static_cast<X86Mir2Lir*>(cu_->cg.get()); in Prepare()
139 X86Mir2Lir* m2l = Prepare(target); in Test()
193 typedef void (X86Mir2Lir::*AsmFn)(MIR*);
199 X86Mir2Lir *m2l = Prepare(target); in TestVectorFn()
226 &X86Mir2Lir::GenAddVector, in TestAddpd()
230 &X86Mir2Lir::GenAddVector, in TestAddpd()
237 &X86Mir2Lir::GenSubtractVector, in TestSubpd()
241 &X86Mir2Lir::GenSubtractVector, in TestSubpd()
248 &X86Mir2Lir::GenMultiplyVector, in TestMulpd()
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Dtarget_x86.cc147 RegLocation X86Mir2Lir::LocCReturn() { in LocCReturn()
151 RegLocation X86Mir2Lir::LocCReturnRef() { in LocCReturnRef()
155 RegLocation X86Mir2Lir::LocCReturnWide() { in LocCReturnWide()
159 RegLocation X86Mir2Lir::LocCReturnFloat() { in LocCReturnFloat()
163 RegLocation X86Mir2Lir::LocCReturnDouble() { in LocCReturnDouble()
249 RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) const { in TargetReg32()
257 RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg()
266 ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon()
273 ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { in GetPCUseDefEncoding()
277 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks()
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Dcall_x86.cc38 void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { in GenLargeSparseSwitch()
58 void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { in GenLargePackedSwitch()
124 void X86Mir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException()
134 void X86Mir2Lir::UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) { in UnconditionallyMarkGCCard()
152 void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence()
254 void X86Mir2Lir::GenExitSequence() { in GenExitSequence()
277 void X86Mir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence()
281 void X86Mir2Lir::GenSpecialEntryForSuspend() { in GenSpecialEntryForSuspend()
315 void X86Mir2Lir::GenSpecialExitForSuspend() { in GenSpecialExitForSuspend()
330 void X86Mir2Lir::GenImplicitNullCheck(RegStorage reg, int opt_flags) { in GenImplicitNullCheck()
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Dutility_x86.cc33 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpFpRegCopy()
60 bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { in InexpensiveConstantInt()
65 bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat()
69 bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong()
74 bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { in InexpensiveConstantDouble()
87 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
113 LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
119 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
126 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
139 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
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Dint_x86.cc37 void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, in GenCmpLong()
99 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
108 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch()
126 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { in OpRegCopyNoInsert()
144 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpRegCopy()
151 void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { in OpRegCopyWide()
212 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
273 void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect()
388 void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch()
451 void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, in GenFusedLongCmpImmBranch()
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Dassemble_x86.cc31 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = {
555 os << X86Mir2Lir::EncodingMap[rhs].name; in operator <<()
639 size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, in ComputeSize()
709 size_t X86Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize()
711 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; in GetInsnSize()
887 void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { in CheckValidByteRegister()
910 void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, in EmitPrefix()
978 void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { in EmitOpcode()
993 void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, in EmitPrefixAndOpcode()
999 void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { in EmitDisp()
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Dfp_x86.cc26 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, in GenArithOpFloat()
77 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
127 void X86Mir2Lir::GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantFloat()
134 void X86Mir2Lir::GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantDouble()
141 void X86Mir2Lir::GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double) { in GenLongToFP()
210 void X86Mir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion()
361 void X86Mir2Lir::GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_do… in GenRemFP()
467 void X86Mir2Lir::GenCmpFP(Instruction::Code code, RegLocation rl_dest, in GenCmpFP()
512 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch()
580 void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat()
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Dcodegen_x86.h31 class X86Mir2Lir FINAL : public Mir2Lir {
70 ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, int n_regs, ...);
74 X86Mir2Lir* const mir_to_lir_;
80 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
980 DISALLOW_COPY_AND_ASSIGN(X86Mir2Lir);