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Searched refs:lir (Results 1 – 24 of 24) sorted by relevance

/art/compiler/dex/quick/mips/
Dassemble_mips.cc592 void MipsMir2Lir::ConvertShortToLongBranch(LIR* lir) { in ConvertShortToLongBranch() argument
595 int opcode = lir->opcode; in ConvertShortToLongBranch()
596 int dalvik_offset = lir->dalvik_offset; in ConvertShortToLongBranch()
619 LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0], in ConvertShortToLongBranch()
620 lir->operands[1], 0, 0, 0, hop_target); in ConvertShortToLongBranch()
621 InsertLIRBefore(lir, hop_branch); in ConvertShortToLongBranch()
624 InsertLIRBefore(lir, curr_pc); in ConvertShortToLongBranch()
627 lir->target); in ConvertShortToLongBranch()
628 InsertLIRBefore(lir, delta_hi); in ConvertShortToLongBranch()
629 InsertLIRBefore(lir, anchor); in ConvertShortToLongBranch()
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Dcodegen_mips.h127 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
128 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, ResourceMask* use_mask,
132 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
135 size_t GetInsnSize(LIR* lir) OVERRIDE;
136 bool IsUnconditionalBranch(LIR* lir);
273 void ConvertShortToLongBranch(LIR* lir);
Dtarget_mips.cc312 void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, ResourceMask* use_mask, in SetupTargetResourceMasks() argument
314 DCHECK(!lir->flags.use_def_invalid); in SetupTargetResourceMasks()
368 std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { in BuildInsnString() argument
385 operand = lir->operands[nc-'0']; in BuildInsnString()
419 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 1), in BuildInsnString()
420 lir->target); in BuildInsnString()
426 int offset_1 = lir->operands[0]; in BuildInsnString()
427 int offset_2 = NEXT_LIR(lir)->operands[0]; in BuildInsnString()
429 (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & ~3) + in BuildInsnString()
884 bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) { in IsUnconditionalBranch() argument
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/art/compiler/dex/quick/arm/
Dassemble_arm.cc1085 uint8_t* ArmMir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs() argument
1087 for (; lir != nullptr; lir = NEXT_LIR(lir)) { in EncodeLIRs()
1088 lir->offset = (write_pos - write_buffer); in EncodeLIRs()
1089 if (!lir->flags.is_nop) { in EncodeLIRs()
1090 int opcode = lir->opcode; in EncodeLIRs()
1094 if (lir->offset & 0x2) { in EncodeLIRs()
1100 } else if (LIKELY(!lir->flags.is_nop)) { in EncodeLIRs()
1101 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; in EncodeLIRs()
1106 operand = lir->operands[i]; in EncodeLIRs()
1241 LIR* lir; in AssembleLIR() local
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Dtarget_arm.cc163 void ArmMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks() argument
166 DCHECK(!lir->flags.use_def_invalid); in SetupTargetResourceMasks()
168 int opcode = lir->opcode; in SetupTargetResourceMasks()
183 def_mask->SetBits(EncodeArmRegList(lir->operands[0])); in SetupTargetResourceMasks()
187 def_mask->SetBits(EncodeArmRegList(lir->operands[1])); in SetupTargetResourceMasks()
191 def_mask->SetBits(EncodeArmRegList(lir->operands[0])); in SetupTargetResourceMasks()
195 for (int i = 0; i < lir->operands[2]; i++) { in SetupTargetResourceMasks()
196 SetupRegMask(def_mask, lir->operands[1] + i); in SetupTargetResourceMasks()
210 use_mask->SetBits(EncodeArmRegList(lir->operands[0])); in SetupTargetResourceMasks()
214 use_mask->SetBits(EncodeArmRegList(lir->operands[1])); in SetupTargetResourceMasks()
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Dcodegen_arm.h127 static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
128 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
129 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
133 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
136 size_t GetInsnSize(LIR* lir) OVERRIDE;
137 bool IsUnconditionalBranch(LIR* lir);
273 size_t GetInstructionOffset(LIR* lir);
Dutility_arm.cc892 LIR* lir = nullptr; in LoadStoreUsingInsnWithOffsetImm8Shl2() local
894 lir = NewLIR3(opcode, r_src_dest.GetReg(), r_ptr.GetReg(), encoded_disp); in LoadStoreUsingInsnWithOffsetImm8Shl2()
896 lir = NewLIR4(opcode, r_src_dest.GetLowReg(), r_src_dest.GetHighReg(), r_ptr.GetReg(), in LoadStoreUsingInsnWithOffsetImm8Shl2()
902 return lir; in LoadStoreUsingInsnWithOffsetImm8Shl2()
1257 size_t ArmMir2Lir::GetInstructionOffset(LIR* lir) { in GetInstructionOffset() argument
1258 uint64_t check_flags = GetTargetInstFlags(lir->opcode); in GetInstructionOffset()
1260 size_t offset = (check_flags & IS_TERTIARY_OP) ? lir->operands[2] : 0; in GetInstructionOffset()
Dint_arm.cc1091 LIR* lir = NewLIR2(kThumb2LdrPcRel12, reg.GetReg(), 0); in OpPcRelLoad() local
1092 lir->target = target; in OpPcRelLoad()
/art/compiler/dex/quick/x86/
Dassemble_x86.cc709 size_t X86Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize() argument
710 DCHECK(!IsPseudoLirOp(lir->opcode)); in GetInsnSize()
711 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; in GetInsnSize()
712 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; in GetInsnSize()
718 return lir->operands[0]; // Length of nop is sole operand. in GetInsnSize()
722 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); in GetInsnSize()
724 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); in GetInsnSize()
726 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); in GetInsnSize()
728 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); in GetInsnSize()
730 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); in GetInsnSize()
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Dquick_assemble_x86_test.cc141 LIR lir; in Test() local
142 memset(&lir, 0, sizeof(LIR)); in Test()
143 lir.opcode = opcode; in Test()
144 lir.operands[0] = op0; in Test()
145 lir.operands[1] = op1; in Test()
146 lir.operands[2] = op2; in Test()
147 lir.operands[3] = op3; in Test()
148 lir.operands[4] = op4; in Test()
149 lir.flags.size = m2l->GetInsnSize(&lir); in Test()
151 AssemblerStatus status = m2l->AssembleInstructions(&lir, 0); in Test()
Dfp_x86.cc653 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP_32.GetReg(), displacement, 0x7fffffff); in GenInlinedAbsFloat() local
654 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); in GenInlinedAbsFloat()
655 AnnotateDalvikRegAccess(lir, displacement >> 2, true /* is_load */, false /* is_64bit*/); in GenInlinedAbsFloat()
717 …LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP_32.GetReg(), displacement + HIWORD_OFFSET, 0x7fffffff); in GenInlinedAbsDouble() local
718 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, true /* is_load */, true /* is_6… in GenInlinedAbsDouble()
719 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /*is_load */, true /* is_6… in GenInlinedAbsDouble()
Dcodegen_x86.h160 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
161 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
165 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE;
168 size_t GetInsnSize(LIR* lir) OVERRIDE;
169 bool IsUnconditionalBranch(LIR* lir) OVERRIDE;
496 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir);
Dint_x86.cc1980 LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), in GenLongRegOrMemOp() local
1982 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
1986 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); in GenLongRegOrMemOp()
1987 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
2023 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, in GenLongArith() local
2025 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, in GenLongArith()
2027 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, in GenLongArith()
2031 lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); in GenLongArith()
2032 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, in GenLongArith()
2034 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, in GenLongArith()
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Dtarget_x86.cc277 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks() argument
280 DCHECK(!lir->flags.use_def_invalid); in SetupTargetResourceMasks()
315 if (lir->opcode == kX86RepneScasw) { in SetupTargetResourceMasks()
357 std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { in BuildInsnString() argument
376 int operand = lir->operands[operand_number]; in BuildInsnString()
387 static_cast<uint32_t>(lir->operands[operand_number+1])); in BuildInsnString()
408 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, in BuildInsnString()
409 lir->target); in BuildInsnString()
810 bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { in IsUnconditionalBranch() argument
811 return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); in IsUnconditionalBranch()
/art/compiler/dex/quick/arm64/
Dassemble_arm64.cc688 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs() argument
690 for (; lir != nullptr; lir = NEXT_LIR(lir)) { in EncodeLIRs()
691 lir->offset = (write_pos - write_buffer); in EncodeLIRs()
692 bool opcode_is_wide = IS_WIDE(lir->opcode); in EncodeLIRs()
693 A64Opcode opcode = UNWIDE(lir->opcode); in EncodeLIRs()
699 if (LIKELY(!lir->flags.is_nop)) { in EncodeLIRs()
708 uint32_t operand = lir->operands[i]; in EncodeLIRs()
785 << " @ 0x" << std::hex << lir->dalvik_offset; in EncodeLIRs()
860 static LIR* GetPrevEmittingLIR(LIR* lir) { in GetPrevEmittingLIR() argument
861 DCHECK(lir != nullptr); in GetPrevEmittingLIR()
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Dtarget_arm64.cc168 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks() argument
171 DCHECK(!lir->flags.use_def_invalid); in SetupTargetResourceMasks()
340 std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { in BuildInsnString() argument
357 operand = lir->operands[nc-'0']; in BuildInsnString()
362 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : in BuildInsnString()
412 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_WIDE(lir->opcode)) ? 'd' : 's', in BuildInsnString()
416 bool is_wide = IS_WIDE(lir->opcode); in BuildInsnString()
458 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); in BuildInsnString()
470 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); in BuildInsnString()
477 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), in BuildInsnString()
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Dcodegen_arm64.h116 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
117 void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
121 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE;
124 size_t GetInsnSize(LIR* lir) OVERRIDE;
125 bool IsUnconditionalBranch(LIR* lir) OVERRIDE;
241 size_t GetInstructionOffset(LIR* lir) OVERRIDE;
350 size_t GetLoadStoreSize(LIR* lir);
358 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
Dutility_arm64.cc92 size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) { in GetLoadStoreSize() argument
93 bool opcode_is_wide = IS_WIDE(lir->opcode); in GetLoadStoreSize()
94 A64Opcode opcode = UNWIDE(lir->opcode); in GetLoadStoreSize()
101 size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) { in GetInstructionOffset() argument
102 size_t offset = lir->operands[2]; in GetInstructionOffset()
103 uint64_t check_flags = GetTargetInstFlags(lir->opcode); in GetInstructionOffset()
107 offset = offset * (1 << GetLoadStoreSize(lir)); in GetInstructionOffset()
Dint_arm64.cc942 LIR* lir = NewLIR2(kA64Ldr2rp, As32BitReg(reg).GetReg(), 0); in OpPcRelLoad() local
943 lir->target = target; in OpPcRelLoad()
/art/compiler/dex/quick/
Dmir_to_lir-inl.h165 inline void Mir2Lir::SetupResourceMasks(LIR* lir) { in SetupResourceMasks() argument
166 int opcode = lir->opcode; in SetupResourceMasks()
169 lir->u.m.use_mask = lir->u.m.def_mask = &kEncodeNone; in SetupResourceMasks()
171 lir->flags.fixup = kFixupLabel; in SetupResourceMasks()
180 lir->flags.fixup = kFixupLabel; in SetupResourceMasks()
184 lir->flags.size = GetInsnSize(lir); in SetupResourceMasks()
185 estimated_native_code_size_ += lir->flags.size; in SetupResourceMasks()
211 lir->u.m.def_mask = lir->u.m.use_mask = &kEncodeAll; in SetupResourceMasks()
216 SetupRegMask(&def_mask, lir->operands[0]); in SetupResourceMasks()
220 SetupRegMask(&def_mask, lir->operands[1]); in SetupResourceMasks()
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Dcodegen_util.cc114 void Mir2Lir::UnlinkLIR(LIR* lir) { in UnlinkLIR() argument
115 if (UNLIKELY(lir == first_lir_insn_)) { in UnlinkLIR()
116 first_lir_insn_ = lir->next; in UnlinkLIR()
117 if (lir->next != nullptr) { in UnlinkLIR()
118 lir->next->prev = nullptr; in UnlinkLIR()
120 DCHECK(lir->next == nullptr); in UnlinkLIR()
121 DCHECK(lir == last_lir_insn_); in UnlinkLIR()
124 } else if (lir == last_lir_insn_) { in UnlinkLIR()
125 last_lir_insn_ = lir->prev; in UnlinkLIR()
126 lir->prev->next = nullptr; in UnlinkLIR()
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Dlocal_optimizations.cc93 inline void Mir2Lir::EliminateLoad(LIR* lir, int reg_id) { in EliminateLoad() argument
94 DCHECK(RegStorage::SameRegType(lir->operands[0], reg_id)); in EliminateLoad()
98 if (lir->operands[0] == reg_id) { in EliminateLoad()
99 NopLIR(lir); in EliminateLoad()
106 dest_reg = RegStorage::Solo32(lir->operands[0]); in EliminateLoad()
110 dest_reg = RegStorage::Solo64(lir->operands[0]); in EliminateLoad()
114 dest_reg = RegStorage::FloatSolo32(lir->operands[0]); in EliminateLoad()
118 dest_reg = RegStorage::FloatSolo64(lir->operands[0]); in EliminateLoad()
125 ConvertMemOpIntoMove(lir, dest_reg, src_reg); in EliminateLoad()
126 NopLIR(lir); in EliminateLoad()
Dmir_to_lir.h190 #define NEXT_LIR(lir) (lir->next) argument
191 #define PREV_LIR(lir) (lir->prev) argument
555 virtual size_t GetInstructionOffset(LIR* lir);
616 void AppendLIR(LIR* lir);
643 void SetupResourceMasks(LIR* lir);
644 void SetMemRefType(LIR* lir, bool is_load, int mem_type);
645 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
649 void EliminateLoad(LIR* lir, int reg_id);
671 void NopLIR(LIR* lir);
672 void UnlinkLIR(LIR* lir);
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Dmir_to_lir.cc1414 size_t Mir2Lir::GetInstructionOffset(LIR* lir) { in GetInstructionOffset() argument
1415 UNUSED(lir); in GetInstructionOffset()