Searched refs:AFGR64RegClass (Results 1 – 9 of 9) sorted by relevance
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()67 const MCRegisterClass *AFGR64RegClass; variable
165 for (RegIter Reg = Mips::AFGR64RegClass.begin(), in getReservedRegs()166 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) in getReservedRegs()
296 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()349 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()431 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
138 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()245 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
260 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize(); in printSavedRegsBitmask()273 } else if (Mips::AFGR64RegClass.contains(Reg)) { in printSavedRegsBitmask()
304 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()650 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()866 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
3338 if (RC == &Mips::AFGR64RegClass) { in parseRegForInlineAsmConstraint()3392 return std::make_pair(0U, &Mips::AFGR64RegClass); in getRegForInlineAsmConstraint()
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
83 AFGR64RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()