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Searched refs:BaseOp (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/R600/
DEvergreenInstructions.td456 field string BaseOp;
465 let BaseOp = name;
471 let BaseOp = name;
487 field string BaseOp;
495 let BaseOp = name;
501 let BaseOp = name;
DR600Instructions.td1740 let RowFields = ["BaseOp"];
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td674 class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
683 let BaseOpcode = BaseOp#"_AbsSet";
710 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
719 let BaseOpcode = BaseOp#"_AbsSet";
1461 multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
1463 let BaseOpcode = "POST_"#BaseOp in {
1582 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1584 let BaseOpcode = BaseOp#_NVJ in {
1645 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1646 let BaseOpcode = BaseOp#_NVJri in {
[all …]
DHexagonInstrInfo.td1490 multiclass JMP_base<string BaseOp, string ExtStr> {
1491 let BaseOpcode = BaseOp in {
1543 multiclass JMPR_base<string BaseOp> {
1544 let BaseOpcode = BaseOp in {
1891 multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
1893 let BaseOpcode = "POST_"#BaseOp in {
3361 multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
3364 let BaseOpcode = "POST_"#BaseOp in {
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1479 const MachineOperand &BaseOp = MI->getOperand(2); in FixInvalidRegPairOp() local
1480 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp()
1501 bool BaseKill = BaseOp.isKill(); in FixInvalidRegPairOp()
1502 bool BaseUndef = BaseOp.isUndef(); in FixInvalidRegPairOp()
/external/llvm/include/llvm/Target/
DTarget.td1149 // let RowFields = BaseOp
1150 // All add instruction predicated/non-predicated will have to set their BaseOp
1153 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1154 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1155 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp16600 unsigned BaseOp = 0; in LowerXALUO() local
16610 BaseOp = X86ISD::INC; in LowerXALUO()
16614 BaseOp = X86ISD::ADD; in LowerXALUO()
16618 BaseOp = X86ISD::ADD; in LowerXALUO()
16626 BaseOp = X86ISD::DEC; in LowerXALUO()
16630 BaseOp = X86ISD::SUB; in LowerXALUO()
16634 BaseOp = X86ISD::SUB; in LowerXALUO()
16638 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL; in LowerXALUO()
16643 BaseOp = X86ISD::UMUL8; in LowerXALUO()
16662 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in LowerXALUO()