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Searched refs:CTTZ (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/Transforms/SimplifyCFG/R600/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dffs-1.ll105 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
106 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
116 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
117 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
127 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 false)
128 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll74 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
75 ; BMI-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
96 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
97 ; BMI-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
118 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
119 ; BMI-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
143 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
144 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
166 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
167 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
[all …]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h326 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp293 case ISD::CTTZ: return "cttz"; in getOperationName()
DLegalizeVectorTypes.cpp74 case ISD::CTTZ: in ScalarizeVectorResult()
613 case ISD::CTTZ: in SplitVectorResult()
1324 case ISD::CTTZ: in SplitVectorOperand()
1798 case ISD::CTTZ: in WidenVectorResult()
DLegalizeDAG.cpp2809 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2810 case ISD::CTTZ: { in ExpandBitCount()
2849 case ISD::CTTZ: in ExpandNode()
4042 case ISD::CTTZ: in PromoteNode()
4052 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
DLegalizeVectorOps.cpp282 case ISD::CTTZ: in LegalizeOp()
DLegalizeIntegerTypes.cpp65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult()
373 if (N->getOpcode() == ISD::CTTZ) { in PromoteIntRes_CTTZ()
1249 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
DSelectionDAG.cpp2184 case ISD::CTTZ: in computeKnownBits()
2778 case ISD::CTTZ: in getNode()
DDAGCombiner.cpp1334 case ISD::CTTZ: return visitCTTZ(N); in visit()
4687 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); in visitCTTZ()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp122 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
123 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp140 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp157 setOperationAction(ISD::CTTZ, VT, Expand); in InitAMDILLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1311 setOperationAction(ISD::CTTZ, VT, Expand); in HexagonTargetLowering()
1730 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in HexagonTargetLowering()
1731 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp252 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering()
253 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in NVPTXTargetLowering()
254 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in NVPTXTargetLowering()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp278 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering()
348 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1474 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1529 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp321 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in MipsTargetLowering()
322 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in MipsTargetLowering()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td377 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); in X86TargetLowering()
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); in X86TargetLowering()
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); in X86TargetLowering()
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); in X86TargetLowering()
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); in X86TargetLowering()
710 setOperationAction(ISD::CTTZ, VT, Expand); in X86TargetLowering()
17243 case ISD::CTTZ: return LowerCTTZ(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
473 setOperationAction(ISD::CTTZ, VT, Expand); in PPCTargetLowering()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp174 setOperationAction(ISD::CTTZ, VT, Expand); in SystemZTargetLowering()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp692 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering()
6303 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()

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