| /external/clang/test/Sema/ |
| D | deref.c | 37 typedef const void CVT; typedef
38 extern CVT cv3;
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| /external/llvm/lib/Target/X86/ |
| D | X86SelectionDAGInfo.cpp | 175 EVT CVT = Count.getValueType(); in EmitTargetCodeForMemset() local
176 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, in EmitTargetCodeForMemset()
177 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); in EmitTargetCodeForMemset()
178 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
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| D | X86SchedHaswell.td | 1818 // CVT(T)PD2DQ.
1820 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVT(T?)PD2DQrr")>;
1822 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVT(T?)PD2DQrm")>;
1828 // CVT(T)PS2PI.
1836 // CVT(T)PD2PI.
1842 def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V?)CVT(T?)SI2SS(64)?rr")>;
1844 // CVT(T)SS2SI.
1846 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rr")>;
1848 def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rm")>;
1856 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rr")>;
[all …]
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| D | X86ISelLowering.cpp | 4971 EVT CVT = Ld.getValueType(); in LowerVectorBroadcast() local
4972 assert(!CVT.isVector() && "Must not broadcast a vector type"); in LowerVectorBroadcast()
4991 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP, in LowerVectorBroadcast()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcher.cpp | 441 if (const CheckValueTypeMatcher *CVT = dyn_cast<CheckValueTypeMatcher>(M)) in isContradictoryImpl() local
442 return CVT->getTypeName() != getTypeName(); in isContradictoryImpl()
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| /external/valgrind/VEX/priv/ |
| D | guest_amd64_toIR.c | 10434 # define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), mkexpr(_t) ) in dis_CVTPD2PS_128() macro
10437 putXMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTPD2PS_128()
10438 putXMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTPD2PS_128()
10439 # undef CVT in dis_CVTPD2PS_128()
10479 # define CVT(_t) \ in dis_CVTxPS2DQ_128() macro
10485 putXMMRegLane32( rG, 3, CVT(t3) ); in dis_CVTxPS2DQ_128()
10486 putXMMRegLane32( rG, 2, CVT(t2) ); in dis_CVTxPS2DQ_128()
10487 putXMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPS2DQ_128()
10488 putXMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPS2DQ_128()
10489 # undef CVT in dis_CVTxPS2DQ_128()
[all …]
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| D | guest_x86_toIR.c | 9679 # define CVT(_t) binop( Iop_F64toF32, \ in disInstr_X86_WRK() macro
9683 putXMMRegLane32F( gregOfRM(modrm), 3, CVT(t3) ); in disInstr_X86_WRK()
9684 putXMMRegLane32F( gregOfRM(modrm), 2, CVT(t2) ); in disInstr_X86_WRK()
9685 putXMMRegLane32F( gregOfRM(modrm), 1, CVT(t1) ); in disInstr_X86_WRK()
9686 putXMMRegLane32F( gregOfRM(modrm), 0, CVT(t0) ); in disInstr_X86_WRK()
9688 # undef CVT in disInstr_X86_WRK()
9722 # define CVT(_t) binop( Iop_F64toI32S, \ in disInstr_X86_WRK() macro
9728 putXMMRegLane32( gregOfRM(modrm), 1, CVT(t1) ); in disInstr_X86_WRK()
9729 putXMMRegLane32( gregOfRM(modrm), 0, CVT(t0) ); in disInstr_X86_WRK()
9731 # undef CVT in disInstr_X86_WRK()
[all …]
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 469 NV50_IR_OPCODE_CASE(ROUND, CVT); in translateOpcode()
504 NV50_IR_OPCODE_CASE(I2F, CVT); in translateOpcode()
522 NV50_IR_OPCODE_CASE(F2I, CVT); in translateOpcode()
531 NV50_IR_OPCODE_CASE(F2U, CVT); in translateOpcode()
532 NV50_IR_OPCODE_CASE(U2F, CVT); in translateOpcode()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 439 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
441 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i6…
548 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?"…
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| /external/icu/icu4c/source/data/zone/ |
| D | tzdbNames.txt | 179 ss{"CVT"}
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.td | 35 // CVT conversion modes
|