Searched refs:Cyclone (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64.td | 35 /// Cyclone has register move instructions which are "free".
39 /// Cyclone has instructions which zero registers for "free".
87 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
88 "Cyclone",
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| D | AArch64SchedCyclone.td | 1 //=- ARMSchedCyclone.td - AArch64 Cyclone Scheduling Defs ----*- tablegen -*-=//
10 // This file defines the machine model for AArch64 Cyclone to support
23 // Define each kind of processor resource and number available on Cyclone.
94 // Define scheduler read/write resources and latency on Cyclone.
242 def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
248 def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
256 def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
304 // Define some longer latency vector op types for Cyclone.
317 // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
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| D | AArch64Subtarget.h | 35 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone}; enumerator
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| /external/llvm/test/CodeGen/ARM/ |
| D | zero-cycle-zero.ll | 67 ; crafted behaviour that we might break in Cyclone.
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| /external/llvm/lib/Target/ARM/ |
| D | ARM.td | 76 // Cyclone has preferred instructions for zeroing VFP registers, which can
471 // Cyclone is very similar to swift
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