1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// AArch64 Subtarget features.
21//
22
23def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
24                                       "Enable ARMv8 FP">;
25
26def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
28
29def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30  "Enable cryptographic instructions">;
31
32def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33  "Enable ARMv8 CRC-32 checksum instructions">;
34
35/// Cyclone has register move instructions which are "free".
36def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
37                                        "Has zero-cycle register moves">;
38
39/// Cyclone has instructions which zero registers for "free".
40def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
41                                        "Has zero-cycle zeroing instructions">;
42
43//===----------------------------------------------------------------------===//
44// Architectures.
45//
46
47def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
48  "Support ARM v8.1a instructions", [FeatureCRC]>;
49
50//===----------------------------------------------------------------------===//
51// Register File Description
52//===----------------------------------------------------------------------===//
53
54include "AArch64RegisterInfo.td"
55include "AArch64CallingConvention.td"
56
57//===----------------------------------------------------------------------===//
58// Instruction Descriptions
59//===----------------------------------------------------------------------===//
60
61include "AArch64Schedule.td"
62include "AArch64InstrInfo.td"
63
64def AArch64InstrInfo : InstrInfo;
65
66//===----------------------------------------------------------------------===//
67// AArch64 Processors supported.
68//
69include "AArch64SchedA53.td"
70include "AArch64SchedA57.td"
71include "AArch64SchedCyclone.td"
72
73def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
74                                   "Cortex-A53 ARM processors",
75                                   [FeatureFPARMv8,
76                                   FeatureNEON,
77                                   FeatureCrypto,
78                                   FeatureCRC]>;
79
80def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
81                                   "Cortex-A57 ARM processors",
82                                   [FeatureFPARMv8,
83                                   FeatureNEON,
84                                   FeatureCrypto,
85                                   FeatureCRC]>;
86
87def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
88                                   "Cyclone",
89                                   [FeatureFPARMv8,
90                                   FeatureNEON,
91                                   FeatureCrypto,
92                                   FeatureCRC,
93                                   FeatureZCRegMove, FeatureZCZeroing]>;
94
95def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
96                                              FeatureNEON,
97                                              FeatureCRC]>;
98
99def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
100def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
101// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
102def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
103def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
104
105//===----------------------------------------------------------------------===//
106// Assembly parser
107//===----------------------------------------------------------------------===//
108
109def GenericAsmParserVariant : AsmParserVariant {
110  int Variant = 0;
111  string Name = "generic";
112}
113
114def AppleAsmParserVariant : AsmParserVariant {
115  int Variant = 1;
116  string Name = "apple-neon";
117}
118
119//===----------------------------------------------------------------------===//
120// Assembly printer
121//===----------------------------------------------------------------------===//
122// AArch64 Uses the MC printer for asm output, so make sure the TableGen
123// AsmWriter bits get associated with the correct class.
124def GenericAsmWriter : AsmWriter {
125  string AsmWriterClassName  = "InstPrinter";
126  int PassSubtarget = 1;
127  int Variant = 0;
128  bit isMCAsmWriter = 1;
129}
130
131def AppleAsmWriter : AsmWriter {
132  let AsmWriterClassName = "AppleInstPrinter";
133  int PassSubtarget = 1;
134  int Variant = 1;
135  int isMCAsmWriter = 1;
136}
137
138//===----------------------------------------------------------------------===//
139// Target Declaration
140//===----------------------------------------------------------------------===//
141
142def AArch64 : Target {
143  let InstructionSet = AArch64InstrInfo;
144  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
145  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
146}
147