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Searched refs:DefIdx (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/CodeGen/
DTargetSchedule.cpp128 unsigned DefIdx = 0; in findDefIdx() local
132 ++DefIdx; in findDefIdx()
134 return DefIdx; in findDefIdx()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
192 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
216 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
235 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in computeInstrLatency() local
236 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
239 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeInstrLatency()
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DPeepholeOptimizer.cpp195 unsigned DefIdx; member in __anon2734e12b0111::ValueTracker
251 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
255 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
266 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker() argument
270 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
272 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
273 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
274 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
521 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
524 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
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DTargetInstrInfo.cpp722 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
732 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
734 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
798 unsigned DefIdx) const { in hasLowDefLatency()
803 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
811 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
815 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
848 const MachineInstr *DefMI, unsigned DefIdx, in computeOperandLatency() argument
859 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
862 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
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DLiveRangeEdit.cpp126 SlotIndex DefIdx; in canRematerializeAt() local
128 DefIdx = LIS.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
130 DefIdx = RM.ParentVNI->def; in canRematerializeAt()
131 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); in canRematerializeAt()
140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
DLiveRangeCalc.cpp46 SlotIndex DefIdx = in createDeadDef() local
50 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
178 unsigned DefIdx; in extendToUses() local
181 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
184 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
DMachineVerifier.cpp884 unsigned DefIdx; in visitMachineOperand() local
886 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
887 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1111 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
1112 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); in checkLiveness()
1115 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { in checkLiveness()
1117 if (VNI->def != DefIdx) { in checkLiveness()
1120 << DefIdx << " in " << LI << '\n'; in checkLiveness()
1124 errs() << DefIdx << " is not live in " << LI << '\n'; in checkLiveness()
1128 LiveQueryResult LRQ = LI.Query(DefIdx); in checkLiveness()
DMachineInstr.cpp757 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
758 if (DefIdx != -1) in addOperand()
759 tieOperands(DefIdx, OpNo); in addOperand()
1040 unsigned DefIdx; in getRegClassConstraint() local
1041 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1042 OpIdx = DefIdx; in getRegClassConstraint()
1234 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1235 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1242 if (DefIdx < TiedMax) in tieOperands()
1243 UseMO.TiedTo = DefIdx + 1; in tieOperands()
DRegisterCoalescer.cpp651 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef() local
652 assert(DefIdx != -1); in removeCopyByCommutingDef()
654 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
755 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef() local
756 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); in removeCopyByCommutingDef()
759 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); in removeCopyByCommutingDef()
760 assert(DVNI->def == DefIdx); in removeCopyByCommutingDef()
763 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx); in removeCopyByCommutingDef()
DInlineSpiller.cpp916 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewVReg, RM, in reMaterializeFor() local
918 (void)DefIdx; in reMaterializeFor()
919 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' in reMaterializeFor()
920 << *LIS.getInstructionFromIndex(DefIdx)); in reMaterializeFor()
DRegAllocFast.cpp743 unsigned DefIdx = 0; in handleThroughOperands() local
744 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; in handleThroughOperands()
746 << DefIdx << ".\n"); in handleThroughOperands()
DMachineLICM.cpp205 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
1048 unsigned DefIdx, unsigned Reg) const { in HasHighOperandLatency() argument
1065 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i)) in HasHighOperandLatency()
/external/llvm/include/llvm/MC/
DMCInstrItineraries.h187 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
191 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
193 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
201 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
208 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
213 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
223 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
DMCSubtargetInfo.h113 unsigned DefIdx) const { in getWriteLatencyEntry() argument
114 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
117 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h56 const MachineInstr &MI, unsigned DefIdx,
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
277 const MachineInstr *DefMI, unsigned DefIdx,
281 SDNode *DefNode, unsigned DefIdx,
303 unsigned DefIdx, unsigned DefAlign) const;
307 unsigned DefIdx, unsigned DefAlign) const;
318 unsigned DefIdx, unsigned DefAlign,
333 const MachineInstr *DefMI, unsigned DefIdx,
338 unsigned DefIdx) const override;
DARMBaseInstrInfo.cpp3124 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3125 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3128 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3165 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3166 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3169 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3268 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3274 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3275 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3284 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
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/external/llvm/include/llvm/Target/
DTargetInstrInfo.h309 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
327 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
347 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
751 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
765 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs() argument
779 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1025 SDNode *DefNode, unsigned DefIdx,
1037 const MachineInstr *DefMI, unsigned DefIdx,
1044 const MachineInstr *DefMI, unsigned DefIdx,
1079 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h99 const MachineInstr *DefMI, unsigned DefIdx,
103 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
111 unsigned DefIdx) const override { in hasLowDefLatency() argument
DPPCInstrInfo.cpp107 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
110 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
113 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); in getOperandLatency()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp205 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
206 DefIdx != DefEnd; ++DefIdx) { in getLatency()
209 DefIdx); in getLatency()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.h136 unsigned DefIdx; variable
154 return DefIdx-1; in GetIdx()
DScheduleDAGSDNodes.cpp556 DefIdx = 0; in InitNodeNumDefs()
562 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
570 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
571 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
573 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
574 ++DefIdx; in Advance()
636 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
640 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
DInstrEmitter.cpp999 unsigned DefIdx = GroupIdx[DefGroup] + 1; in EmitSpecialNode() local
1002 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h175 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
DMachineInstr.h985 void tieOperands(unsigned DefIdx, unsigned UseIdx);
/external/llvm/lib/Target/X86/
DX86InstrInfo.h425 const MachineInstr *DefMI, unsigned DefIdx,

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