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Searched refs:DstRC (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp186 const TargetRegisterClass *DstRC in isVGPRToSGPRCopy() local
194 DstRC == &AMDGPU::M0RegRegClass || in isVGPRToSGPRCopy()
199 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
320 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
321 DstRC = MRI.getRegClass(MI.getOperand(0).getReg()); in runOnMachineFunction()
324 if (TRI->isSGPRClass(DstRC) && in runOnMachineFunction()
DSILowerI1Copies.cpp106 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction() local
109 if (DstRC == &AMDGPU::VReg_1RegClass && in runOnMachineFunction()
136 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) && in runOnMachineFunction()
DSIInstrInfo.cpp449 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { in getMovOpcode()
451 if (DstRC->getSize() == 4) { in getMovOpcode()
452 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
453 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
455 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
1763 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in legalizeOperands() local
1765 if (DstRC != Src0RC) { in legalizeOperands()
1767 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC); in legalizeOperands()
DSIInstrInfo.h116 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
DSIInstrInfo.td916 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
926 field dag Outs = (outs DstRC:$dst);
1562 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1594 (outs P.DstRC.RegClass:$dst),
/external/llvm/utils/TableGen/
DFastISelEmitter.cpp193 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
275 if (DstRC) { in initialize()
276 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
279 DstRC = RC; in initialize()
481 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
489 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
490 if (!DstRC) in collectPatterns()
529 DstRC)) in collectPatterns()
580 DstRC, in collectPatterns()
/external/llvm/lib/Target/X86/
DX86InstrMMX.td185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
191 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
192 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>,
197 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
203 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
[all …]
DX86InstrAVX512.td778 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
780 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
782 [(set DstRC:$dst,
784 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
788 [(set DstRC:$dst,
792 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
794 [(set DstRC:$dst,
796 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
800 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
3880 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
[all …]
DX86InstrSSE.td1480 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1483 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1484 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1486 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1487 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1491 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1495 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1498 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1503 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1506 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
[all …]
DX86InstrInfo.cpp5503 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand() local
5508 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
5575 const TargetRegisterClass *DstRC = nullptr; in unfoldMemoryOperand() local
5577 DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand()
5578 VTs.push_back(*DstRC->vt_begin()); in unfoldMemoryOperand()
5609 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), in unfoldMemoryOperand()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
164 DstRC = UseRC; in EmitCopyFromReg()
166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
175 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
333 const TargetRegisterClass *DstRC = nullptr; in AddRegisterOperand() local
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in AddRegisterOperand()
590 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
[all …]
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
146 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
151 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
156 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
DMipsMSAInstrInfo.td3578 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3580 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3635 RegisterClass DstRC, MSAInst Insn,
3639 DstRC),
3643 RegisterClass DstRC, MSAInst Insn,
3647 DstRC),
3651 RegisterClass DstRC> :
3652 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3655 RegisterClass DstRC> :
3656 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
DMipsInstrInfo.td938 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
939 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
940 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
949 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
950 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
951 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
DMipsDSPInstrInfo.td1278 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp122 const TargetRegisterClass *DstRC = in processBlock() local
130 unsigned NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp332 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
333 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
334 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY()
440 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
DRegisterCoalescer.cpp333 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
341 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
348 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
352 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
355 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
370 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1243 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
1248 std::swap(SrcRC, DstRC); in joinCopy()
1250 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx, in joinCopy()
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h184 const TargetRegisterClass *DstRC,
DARMBaseRegisterInfo.cpp769 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
780 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
788 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()
DARMFastISel.cpp2045 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local
2046 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
2065 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
2067 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h844 const TargetRegisterClass *DstRC, in shouldCoalesce() argument