1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips MSA ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 49def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 50def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 51def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 52def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 53def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 54def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 55def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 56def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 57 58def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 59def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 60 61def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 63def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 65 66// Operands 67 68// The immediate of an LSA instruction needs special handling 69// as the encoded value should be subtracted by one. 70def uimm2LSAAsmOperand : AsmOperandClass { 71 let Name = "LSAImm"; 72 let ParserMethod = "parseLSAImm"; 73 let RenderMethod = "addImmOperands"; 74} 75 76def LSAImm : Operand<i32> { 77 let PrintMethod = "printUnsignedImm"; 78 let EncoderMethod = "getLSAImmEncoding"; 79 let DecoderMethod = "DecodeLSAImm"; 80 let ParserMatchClass = uimm2LSAAsmOperand; 81} 82 83def uimm4 : Operand<i32> { 84 let PrintMethod = "printUnsignedImm8"; 85} 86 87def uimm8 : Operand<i32> { 88 let PrintMethod = "printUnsignedImm8"; 89} 90 91def simm5 : Operand<i32>; 92 93def vsplat_uimm1 : Operand<vAny> { 94 let PrintMethod = "printUnsignedImm8"; 95} 96 97def vsplat_uimm2 : Operand<vAny> { 98 let PrintMethod = "printUnsignedImm8"; 99} 100 101def vsplat_uimm3 : Operand<vAny> { 102 let PrintMethod = "printUnsignedImm8"; 103} 104 105def vsplat_uimm4 : Operand<vAny> { 106 let PrintMethod = "printUnsignedImm8"; 107} 108 109def vsplat_uimm5 : Operand<vAny> { 110 let PrintMethod = "printUnsignedImm8"; 111} 112 113def vsplat_uimm6 : Operand<vAny> { 114 let PrintMethod = "printUnsignedImm8"; 115} 116 117def vsplat_uimm8 : Operand<vAny> { 118 let PrintMethod = "printUnsignedImm8"; 119} 120 121def vsplat_simm5 : Operand<vAny>; 122 123def vsplat_simm10 : Operand<vAny>; 124 125def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 126 127// Pattern fragments 128def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 129 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 130def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 131 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 132def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 133 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 134def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 135 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 136 137def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 138 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 139def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 140 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 141def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 142 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 143def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 144 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 145 146def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 147 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 148def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 149 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 150def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 151 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 152def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 153 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 154 155def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 156 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 157def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 158 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 159def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 160 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 161def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 162 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 163 164class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 165 PatFrag<(ops node:$lhs, node:$rhs), 166 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 167 168// ISD::SETFALSE cannot occur 169def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 170def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 171def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 172def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 173def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 174def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 175def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 176def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 177def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 178def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 179def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 180def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 181def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 182def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 183def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 184def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 185def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 186def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 187def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 188def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 189def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 190def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 191def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 192def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 193def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 194def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 195def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 196def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 197// ISD::SETTRUE cannot occur 198// ISD::SETFALSE2 cannot occur 199// ISD::SETTRUE2 cannot occur 200 201class vsetcc_type<ValueType ResTy, CondCode CC> : 202 PatFrag<(ops node:$lhs, node:$rhs), 203 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 204 205def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 206def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 207def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 208def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 209def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 210def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 211def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 212def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 213def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 214def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 215def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 216def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 217def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 218def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 219def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 220def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 221def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 222def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 223def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 224def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 225 226def vsplati8 : PatFrag<(ops node:$e0), 227 (v16i8 (build_vector node:$e0, node:$e0, 228 node:$e0, node:$e0, 229 node:$e0, node:$e0, 230 node:$e0, node:$e0, 231 node:$e0, node:$e0, 232 node:$e0, node:$e0, 233 node:$e0, node:$e0, 234 node:$e0, node:$e0))>; 235def vsplati16 : PatFrag<(ops node:$e0), 236 (v8i16 (build_vector node:$e0, node:$e0, 237 node:$e0, node:$e0, 238 node:$e0, node:$e0, 239 node:$e0, node:$e0))>; 240def vsplati32 : PatFrag<(ops node:$e0), 241 (v4i32 (build_vector node:$e0, node:$e0, 242 node:$e0, node:$e0))>; 243def vsplati64 : PatFrag<(ops node:$e0), 244 (v2i64 (build_vector node:$e0, node:$e0))>; 245def vsplatf32 : PatFrag<(ops node:$e0), 246 (v4f32 (build_vector node:$e0, node:$e0, 247 node:$e0, node:$e0))>; 248def vsplatf64 : PatFrag<(ops node:$e0), 249 (v2f64 (build_vector node:$e0, node:$e0))>; 250 251def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 252 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 253def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 254 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 255def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 256 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 257def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 258 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; 259 260class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 261 SDNodeXForm xform = NOOP_SDNodeXForm> 262 : PatLeaf<frag, pred, xform> { 263 Operand OpClass = opclass; 264} 265 266class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 267 list<SDNode> roots = [], 268 list<SDNodeProperty> props = []> : 269 ComplexPattern<ty, numops, fn, roots, props> { 270 Operand OpClass = opclass; 271} 272 273def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 274 "selectVSplatUimm3", 275 [build_vector, bitconvert]>; 276 277def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 278 "selectVSplatUimm4", 279 [build_vector, bitconvert]>; 280 281def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 282 "selectVSplatUimm5", 283 [build_vector, bitconvert]>; 284 285def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 286 "selectVSplatUimm8", 287 [build_vector, bitconvert]>; 288 289def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 290 "selectVSplatSimm5", 291 [build_vector, bitconvert]>; 292 293def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 294 "selectVSplatUimm3", 295 [build_vector, bitconvert]>; 296 297def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 298 "selectVSplatUimm4", 299 [build_vector, bitconvert]>; 300 301def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 302 "selectVSplatUimm5", 303 [build_vector, bitconvert]>; 304 305def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 306 "selectVSplatSimm5", 307 [build_vector, bitconvert]>; 308 309def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 310 "selectVSplatUimm2", 311 [build_vector, bitconvert]>; 312 313def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 314 "selectVSplatUimm5", 315 [build_vector, bitconvert]>; 316 317def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 318 "selectVSplatSimm5", 319 [build_vector, bitconvert]>; 320 321def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 322 "selectVSplatUimm1", 323 [build_vector, bitconvert]>; 324 325def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 326 "selectVSplatUimm5", 327 [build_vector, bitconvert]>; 328 329def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 330 "selectVSplatUimm6", 331 [build_vector, bitconvert]>; 332 333def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 334 "selectVSplatSimm5", 335 [build_vector, bitconvert]>; 336 337// Any build_vector that is a constant splat with a value that is an exact 338// power of 2 339def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 340 [build_vector, bitconvert]>; 341 342// Any build_vector that is a constant splat with a value that is the bitwise 343// inverse of an exact power of 2 344def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 345 [build_vector, bitconvert]>; 346 347// Any build_vector that is a constant splat with only a consecutive sequence 348// of left-most bits set. 349def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 350 "selectVSplatMaskL", 351 [build_vector, bitconvert]>; 352 353// Any build_vector that is a constant splat with only a consecutive sequence 354// of right-most bits set. 355def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1, 356 "selectVSplatMaskR", 357 [build_vector, bitconvert]>; 358 359// Any build_vector that is a constant splat with a value that equals 1 360// FIXME: These should be a ComplexPattern but we can't use them because the 361// ISel generator requires the uses to have a name, but providing a name 362// causes other errors ("used in pattern but not operand list") 363def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 364 APInt Imm; 365 EVT EltTy = N->getValueType(0).getVectorElementType(); 366 367 return selectVSplat (N, Imm) && 368 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 369}]>; 370 371def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 372 APInt Imm; 373 SDNode *BV = N->getOperand(0).getNode(); 374 EVT EltTy = N->getValueType(0).getVectorElementType(); 375 376 return selectVSplat (BV, Imm) && 377 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 378}]>; 379 380def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 381 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 382 immAllOnesV))>; 383def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 384 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 385 immAllOnesV))>; 386def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 387 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 388 immAllOnesV))>; 389def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 390 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 391 node:$wt), 392 (bitconvert (v4i32 immAllOnesV))))>; 393 394def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 395 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 396def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 397 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 398def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 399 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 400def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 401 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 402 node:$wt))>; 403 404def vbset_b : PatFrag<(ops node:$ws, node:$wt), 405 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 406def vbset_h : PatFrag<(ops node:$ws, node:$wt), 407 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 408def vbset_w : PatFrag<(ops node:$ws, node:$wt), 409 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 410def vbset_d : PatFrag<(ops node:$ws, node:$wt), 411 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 412 node:$wt))>; 413 414def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), 415 (fsub node:$wd, (fmul node:$ws, node:$wt))>; 416 417def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 418 (add node:$wd, (mul node:$ws, node:$wt))>; 419 420def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 421 (sub node:$wd, (mul node:$ws, node:$wt))>; 422 423def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 424 (fmul node:$ws, (fexp2 node:$wt))>; 425 426// Immediates 427def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>; 428def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>; 429 430// Instruction encoding. 431class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 432class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 433class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 434class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 435 436class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 437class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 438class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 439class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 440 441class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 442class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 443class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 444class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 445 446class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 447class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 448class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 449class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 450 451class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 452class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 453class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 454class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 455 456class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 457class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 458class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 459class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 460 461class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 462 463class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 464 465class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 466class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 467class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 468class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 469 470class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 471class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 472class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 473class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 474 475class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 476class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 477class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 478class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 479 480class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 481class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 482class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 483class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 484 485class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 486class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 487class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 488class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 489 490class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 491class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 492class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 493class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 494 495class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 496class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 497class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 498class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 499 500class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 501class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 502class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 503class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 504 505class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 506class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 507class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 508class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 509 510class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 511class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 512class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 513class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 514 515class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 516class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 517class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 518class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 519 520class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 521class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 522class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 523class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 524 525class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 526 527class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 528 529class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 530 531class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 532 533class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 534class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 535class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 536class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 537 538class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 539class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 540class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 541class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 542 543class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 544class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 545class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 546class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 547 548class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 549 550class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 551 552class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 553 554class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 555class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 556class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 557class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 558 559class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 560class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 561class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 562class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 563 564class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 565class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 566class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 567class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 568 569class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 570 571class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 572class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 573class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 574class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 575 576class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 577class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 578class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 579class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 580 581class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 582 583class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 584class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 585class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 586class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 587 588class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 589class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 590class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 591class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 592 593class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 594class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 595class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 596class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 597 598class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 599class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 600class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 601class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 602 603class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 604class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 605class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 606class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 607 608class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 609class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 610class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 611class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 612 613class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 614class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 615class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 616class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 617 618class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 619class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 620class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 621class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 622 623class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 624class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 625class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 626class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 627 628class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 629class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 630class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 631class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>; 632 633class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 634 635class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 636class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 637class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 638class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 639 640class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 641class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 642class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 643class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 644 645class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 646class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 647class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 648 649class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 650class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 651class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 652 653class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 654class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 655class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 656 657class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 658class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 659class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 660 661class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 662class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 663class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 664 665class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 666class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 667class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 668 669class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 670class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 671 672class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 673class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 674 675class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 676class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 677 678class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 679class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 680 681class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 682class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 683 684class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 685class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 686 687class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 688class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 689 690class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 691class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 692 693class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 694class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 695 696class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 697class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 698 699class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 700class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 701 702class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 703class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 704 705class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 706class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 707 708class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 709class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 710 711class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 712class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 713 714class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 715class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 716 717class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 718class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 719 720class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 721class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 722 723class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 724class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 725 726class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 727class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 728 729class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 730class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 731 732class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 733class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 734 735class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 736class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 737class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 738class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 739 740class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 741class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 742 743class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 744class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 745 746class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 747class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 748 749class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 750class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 751 752class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 753class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 754 755class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 756class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 757 758class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 759class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 760 761class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 762class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 763 764class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 765class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 766 767class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 768class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 769 770class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 771class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 772 773class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 774class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 775 776class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 777class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 778 779class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 780class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 781 782class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 783class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 784 785class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 786class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 787 788class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 789class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 790 791class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 792class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 793 794class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 795class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 796 797class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 798class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 799 800class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 801class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 802 803class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 804class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 805 806class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 807class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 808 809class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 810class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 811 812class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 813class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 814 815class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 816class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 817 818class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 819class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 820 821class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 822class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 823 824class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 825class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 826 827class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 828class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 829class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 830 831class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 832class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 833class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 834 835class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 836class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 837class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 838 839class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 840class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 841class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 842 843class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 844class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 845class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 846class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 847 848class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 849class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 850class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 851class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 852 853class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 854class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 855class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 856class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 857 858class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 859class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 860class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 861class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 862 863class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 864class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 865class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 866class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 867 868class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 869class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 870class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 871class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 872 873class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 874class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 875class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 876class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 877 878class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 879class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 880class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 881class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 882 883class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 884class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 885 886class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 887class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 888 889class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 890class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 891 892class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 893class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 894class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 895class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 896 897class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 898class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 899class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 900class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 901 902class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 903class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 904class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 905class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 906 907class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 908class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 909class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 910class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 911 912class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 913class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 914class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 915class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 916 917class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 918class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 919class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 920class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 921 922class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 923class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 924class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 925class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 926 927class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 928class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 929class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 930class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 931 932class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 933class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 934class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 935class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 936 937class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 938class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 939class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 940class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 941 942class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 943class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 944class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 945class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 946 947class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 948class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 949class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 950class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 951 952class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 953class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 954class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 955class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 956 957class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 958 959class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 960class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 961 962class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 963class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 964 965class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 966class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 967class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 968class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 969 970class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 971class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 972 973class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 974class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 975 976class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 977class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 978class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 979class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 980 981class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 982class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 983class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 984class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 985 986class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 987class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 988class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 989class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 990 991class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 992 993class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 994 995class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 996 997class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 998 999class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 1000class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 1001class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 1002class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 1003 1004class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 1005class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 1006class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 1007class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 1008 1009class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 1010class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 1011class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 1012class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 1013 1014class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 1015class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 1016class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 1017class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 1018 1019class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 1020class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 1021class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 1022class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 1023 1024class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 1025class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 1026class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 1027 1028class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 1029class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 1030class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 1031class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 1032 1033class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 1034class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1035class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1036class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1037 1038class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1039class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1040class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1041class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1042 1043class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1044class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1045class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1046class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1047 1048class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1049class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1050class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1051class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1052 1053class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1054class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1055class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1056class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1057 1058class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1059class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1060class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1061class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1062 1063class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1064class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1065class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1066class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1067 1068class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1069class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1070class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1071class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1072 1073class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1074class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1075class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1076class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1077 1078class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1079class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1080class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1081class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1082 1083class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1084class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1085class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1086class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1087 1088class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1089class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1090class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1091class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1092 1093class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1094class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1095class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1096class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1097 1098class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1099class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1100class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1101class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1102 1103class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1104class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1105class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1106class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1107 1108class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1109class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1110class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1111class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1112 1113class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1114class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1115class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1116class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1117 1118class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1119class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1120class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1121class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1122 1123class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1124class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1125class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1126class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1127 1128class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1129class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1130class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1131class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1132 1133class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1134class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1135class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1136class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1137 1138class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1139 1140class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1141 1142// Instruction desc. 1143class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1144 ComplexPattern Imm, RegisterOperand ROWD, 1145 RegisterOperand ROWS = ROWD, 1146 InstrItinClass itin = NoItinerary> { 1147 dag OutOperandList = (outs ROWD:$wd); 1148 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1149 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1150 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1151 InstrItinClass Itinerary = itin; 1152} 1153 1154class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1155 ComplexPattern Imm, RegisterOperand ROWD, 1156 RegisterOperand ROWS = ROWD, 1157 InstrItinClass itin = NoItinerary> { 1158 dag OutOperandList = (outs ROWD:$wd); 1159 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1160 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1161 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1162 InstrItinClass Itinerary = itin; 1163} 1164 1165class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1166 ComplexPattern Imm, RegisterOperand ROWD, 1167 RegisterOperand ROWS = ROWD, 1168 InstrItinClass itin = NoItinerary> { 1169 dag OutOperandList = (outs ROWD:$wd); 1170 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1171 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1172 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1173 InstrItinClass Itinerary = itin; 1174} 1175 1176class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1177 ComplexPattern Imm, RegisterOperand ROWD, 1178 RegisterOperand ROWS = ROWD, 1179 InstrItinClass itin = NoItinerary> { 1180 dag OutOperandList = (outs ROWD:$wd); 1181 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1182 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1183 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1184 InstrItinClass Itinerary = itin; 1185} 1186 1187// This class is deprecated and will be removed soon. 1188class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1189 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1190 InstrItinClass itin = NoItinerary> { 1191 dag OutOperandList = (outs ROWD:$wd); 1192 dag InOperandList = (ins ROWS:$ws, uimm3:$m); 1193 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1194 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))]; 1195 InstrItinClass Itinerary = itin; 1196} 1197 1198// This class is deprecated and will be removed soon. 1199class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1200 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1201 InstrItinClass itin = NoItinerary> { 1202 dag OutOperandList = (outs ROWD:$wd); 1203 dag InOperandList = (ins ROWS:$ws, uimm4:$m); 1204 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1205 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))]; 1206 InstrItinClass Itinerary = itin; 1207} 1208 1209// This class is deprecated and will be removed soon. 1210class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1211 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1212 InstrItinClass itin = NoItinerary> { 1213 dag OutOperandList = (outs ROWD:$wd); 1214 dag InOperandList = (ins ROWS:$ws, uimm5:$m); 1215 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1216 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))]; 1217 InstrItinClass Itinerary = itin; 1218} 1219 1220// This class is deprecated and will be removed soon. 1221class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1222 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1223 InstrItinClass itin = NoItinerary> { 1224 dag OutOperandList = (outs ROWD:$wd); 1225 dag InOperandList = (ins ROWS:$ws, uimm6:$m); 1226 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1227 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))]; 1228 InstrItinClass Itinerary = itin; 1229} 1230 1231class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1232 ComplexPattern Mask, RegisterOperand ROWD, 1233 RegisterOperand ROWS = ROWD, 1234 InstrItinClass itin = NoItinerary> { 1235 dag OutOperandList = (outs ROWD:$wd); 1236 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); 1237 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1238 // Note that binsxi and vselect treat the condition operand the opposite 1239 // way to each other. 1240 // (vselect cond, if_set, if_clear) 1241 // (BSEL_V cond, if_clear, if_set) 1242 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1243 ROWS:$wd_in))]; 1244 InstrItinClass Itinerary = itin; 1245 string Constraints = "$wd = $wd_in"; 1246} 1247 1248class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1249 RegisterOperand ROWD, 1250 RegisterOperand ROWS = ROWD, 1251 InstrItinClass itin = NoItinerary> : 1252 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>; 1253 1254class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1255 RegisterOperand ROWD, 1256 RegisterOperand ROWS = ROWD, 1257 InstrItinClass itin = NoItinerary> : 1258 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>; 1259 1260class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1261 SplatComplexPattern SplatImm, 1262 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1263 InstrItinClass itin = NoItinerary> { 1264 dag OutOperandList = (outs ROWD:$wd); 1265 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1266 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1267 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1268 InstrItinClass Itinerary = itin; 1269} 1270 1271class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1272 ValueType VecTy, RegisterOperand ROD, 1273 RegisterOperand ROWS, 1274 InstrItinClass itin = NoItinerary> { 1275 dag OutOperandList = (outs ROD:$rd); 1276 dag InOperandList = (ins ROWS:$ws, uimm4:$n); 1277 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1278 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))]; 1279 InstrItinClass Itinerary = itin; 1280} 1281 1282class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1283 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1284 InstrItinClass itin = NoItinerary> { 1285 dag OutOperandList = (outs ROWD:$wd); 1286 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n); 1287 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1288 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1289 immZExt4:$n))]; 1290 string Constraints = "$wd = $wd_in"; 1291 InstrItinClass Itinerary = itin; 1292} 1293 1294class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1295 RegisterClass RCD, RegisterClass RCWS> : 1296 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n), 1297 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> { 1298 bit usesCustomInserter = 1; 1299} 1300 1301class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1302 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1303 RegisterOperand ROWS = ROWD, 1304 InstrItinClass itin = NoItinerary> { 1305 dag OutOperandList = (outs ROWD:$wd); 1306 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1307 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1308 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1309 InstrItinClass Itinerary = itin; 1310} 1311 1312class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1313 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1314 RegisterOperand ROWS = ROWD, 1315 InstrItinClass itin = NoItinerary> { 1316 dag OutOperandList = (outs ROWD:$wd); 1317 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1318 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1319 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1320 InstrItinClass Itinerary = itin; 1321} 1322 1323class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1324 RegisterOperand ROWS = ROWD, 1325 InstrItinClass itin = NoItinerary> { 1326 dag OutOperandList = (outs ROWD:$wd); 1327 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1328 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1329 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1330 InstrItinClass Itinerary = itin; 1331} 1332 1333class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1334 InstrItinClass itin = NoItinerary> { 1335 dag OutOperandList = (outs ROWD:$wd); 1336 dag InOperandList = (ins vsplat_simm10:$s10); 1337 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1338 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1339 list<dag> Pattern = []; 1340 bit hasSideEffects = 0; 1341 InstrItinClass Itinerary = itin; 1342} 1343 1344class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1345 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1346 InstrItinClass itin = NoItinerary> { 1347 dag OutOperandList = (outs ROWD:$wd); 1348 dag InOperandList = (ins ROWS:$ws); 1349 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1350 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1351 InstrItinClass Itinerary = itin; 1352} 1353 1354class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1355 SDPatternOperator OpNode, RegisterOperand ROWD, 1356 RegisterOperand ROS = ROWD, 1357 InstrItinClass itin = NoItinerary> { 1358 dag OutOperandList = (outs ROWD:$wd); 1359 dag InOperandList = (ins ROS:$rs); 1360 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1361 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1362 InstrItinClass Itinerary = itin; 1363} 1364 1365class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1366 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1367 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1368 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1369 let usesCustomInserter = 1; 1370} 1371 1372class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1373 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1374 InstrItinClass itin = NoItinerary> { 1375 dag OutOperandList = (outs ROWD:$wd); 1376 dag InOperandList = (ins ROWS:$ws); 1377 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1378 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1379 InstrItinClass Itinerary = itin; 1380} 1381 1382class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1383 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1384 RegisterOperand ROWT = ROWD, 1385 InstrItinClass itin = NoItinerary> { 1386 dag OutOperandList = (outs ROWD:$wd); 1387 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1388 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1389 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1390 InstrItinClass Itinerary = itin; 1391} 1392 1393class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1394 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1395 RegisterOperand ROWT = ROWD, 1396 InstrItinClass itin = NoItinerary> { 1397 dag OutOperandList = (outs ROWD:$wd); 1398 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1399 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1400 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1401 ROWT:$wt))]; 1402 string Constraints = "$wd = $wd_in"; 1403 InstrItinClass Itinerary = itin; 1404} 1405 1406class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1407 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1408 InstrItinClass itin = NoItinerary> { 1409 dag OutOperandList = (outs ROWD:$wd); 1410 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1411 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1412 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1413 InstrItinClass Itinerary = itin; 1414} 1415 1416class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1417 RegisterOperand ROWS = ROWD, 1418 RegisterOperand ROWT = ROWD, 1419 InstrItinClass itin = NoItinerary> { 1420 dag OutOperandList = (outs ROWD:$wd); 1421 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1422 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1423 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1424 ROWT:$wt))]; 1425 string Constraints = "$wd = $wd_in"; 1426 InstrItinClass Itinerary = itin; 1427} 1428 1429class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1430 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1431 InstrItinClass itin = NoItinerary> { 1432 dag OutOperandList = (outs ROWD:$wd); 1433 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1434 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1435 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1436 GPR32Opnd:$rt))]; 1437 InstrItinClass Itinerary = itin; 1438 string Constraints = "$wd = $wd_in"; 1439} 1440 1441class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1442 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1443 RegisterOperand ROWT = ROWD, 1444 InstrItinClass itin = NoItinerary> { 1445 dag OutOperandList = (outs ROWD:$wd); 1446 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1447 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1448 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1449 ROWT:$wt))]; 1450 InstrItinClass Itinerary = itin; 1451 string Constraints = "$wd = $wd_in"; 1452} 1453 1454class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1455 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1456 RegisterOperand ROWT = ROWD, 1457 InstrItinClass itin = NoItinerary> : 1458 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1459 1460class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1461 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1462 RegisterOperand ROWT = ROWD, 1463 InstrItinClass itin = NoItinerary> : 1464 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1465 1466class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1467 dag OutOperandList = (outs); 1468 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1469 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1470 list<dag> Pattern = []; 1471 InstrItinClass Itinerary = IIBranch; 1472 bit isBranch = 1; 1473 bit isTerminator = 1; 1474 bit hasDelaySlot = 1; 1475 list<Register> Defs = [AT]; 1476} 1477 1478class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1479 RegisterOperand ROWD, RegisterOperand ROS, 1480 InstrItinClass itin = NoItinerary> { 1481 dag OutOperandList = (outs ROWD:$wd); 1482 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6:$n); 1483 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1484 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1485 ROS:$rs, 1486 immZExt6:$n))]; 1487 InstrItinClass Itinerary = itin; 1488 string Constraints = "$wd = $wd_in"; 1489} 1490 1491class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1492 RegisterOperand ROWD, RegisterOperand ROFS> : 1493 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs), 1494 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1495 immZExt6:$n))]> { 1496 bit usesCustomInserter = 1; 1497 string Constraints = "$wd = $wd_in"; 1498} 1499 1500class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1501 RegisterOperand ROWD, RegisterOperand ROFS> : 1502 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, GPR32Opnd:$n, ROFS:$fs), 1503 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1504 GPR32Opnd:$n))]> { 1505 bit usesCustomInserter = 1; 1506 string Constraints = "$wd = $wd_in"; 1507} 1508 1509class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1510 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1511 InstrItinClass itin = NoItinerary> { 1512 dag OutOperandList = (outs ROWD:$wd); 1513 dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2); 1514 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1515 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1516 immZExt6:$n, 1517 ROWS:$ws, 1518 immz:$n2))]; 1519 InstrItinClass Itinerary = itin; 1520 string Constraints = "$wd = $wd_in"; 1521} 1522 1523class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1524 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1525 RegisterOperand ROWT = ROWD, 1526 InstrItinClass itin = NoItinerary> { 1527 dag OutOperandList = (outs ROWD:$wd); 1528 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1529 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1530 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1531 InstrItinClass Itinerary = itin; 1532} 1533 1534class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1535 RegisterOperand ROWD, 1536 RegisterOperand ROWS = ROWD, 1537 InstrItinClass itin = NoItinerary> { 1538 dag OutOperandList = (outs ROWD:$wd); 1539 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1540 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1541 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1542 ROWS:$ws))]; 1543 InstrItinClass Itinerary = itin; 1544} 1545 1546class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1547 RegisterOperand ROWS = ROWD, 1548 RegisterOperand ROWT = ROWD> : 1549 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1550 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1551 1552class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1553 IsCommutable; 1554class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1555 IsCommutable; 1556class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1557 IsCommutable; 1558class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1559 IsCommutable; 1560 1561class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1562 MSA128BOpnd>, IsCommutable; 1563class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1564 MSA128HOpnd>, IsCommutable; 1565class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1566 MSA128WOpnd>, IsCommutable; 1567class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1568 MSA128DOpnd>, IsCommutable; 1569 1570class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1571 MSA128BOpnd>, IsCommutable; 1572class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1573 MSA128HOpnd>, IsCommutable; 1574class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1575 MSA128WOpnd>, IsCommutable; 1576class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1577 MSA128DOpnd>, IsCommutable; 1578 1579class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1580 MSA128BOpnd>, IsCommutable; 1581class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1582 MSA128HOpnd>, IsCommutable; 1583class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1584 MSA128WOpnd>, IsCommutable; 1585class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1586 MSA128DOpnd>, IsCommutable; 1587 1588class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1589class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1590class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1591class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1592 1593class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1594 MSA128BOpnd>; 1595class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1596 MSA128HOpnd>; 1597class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1598 MSA128WOpnd>; 1599class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1600 MSA128DOpnd>; 1601 1602class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1603class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1604class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1605class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1606 1607class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1608 MSA128BOpnd>; 1609 1610class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1611 MSA128BOpnd>; 1612class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1613 MSA128HOpnd>; 1614class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1615 MSA128WOpnd>; 1616class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1617 MSA128DOpnd>; 1618 1619class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1620 MSA128BOpnd>; 1621class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1622 MSA128HOpnd>; 1623class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1624 MSA128WOpnd>; 1625class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1626 MSA128DOpnd>; 1627 1628class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1629 IsCommutable; 1630class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1631 IsCommutable; 1632class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1633 IsCommutable; 1634class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1635 IsCommutable; 1636 1637class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1638 IsCommutable; 1639class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1640 IsCommutable; 1641class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1642 IsCommutable; 1643class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1644 IsCommutable; 1645 1646class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1647 MSA128BOpnd>, IsCommutable; 1648class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1649 MSA128HOpnd>, IsCommutable; 1650class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1651 MSA128WOpnd>, IsCommutable; 1652class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1653 MSA128DOpnd>, IsCommutable; 1654 1655class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1656 MSA128BOpnd>, IsCommutable; 1657class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1658 MSA128HOpnd>, IsCommutable; 1659class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1660 MSA128WOpnd>, IsCommutable; 1661class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1662 MSA128DOpnd>, IsCommutable; 1663 1664class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1665class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1666class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1667class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1668 1669class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1670 MSA128BOpnd>; 1671class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1672 MSA128HOpnd>; 1673class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1674 MSA128WOpnd>; 1675class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1676 MSA128DOpnd>; 1677 1678class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1679 MSA128BOpnd>; 1680class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1681 MSA128HOpnd>; 1682class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1683 MSA128WOpnd>; 1684class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1685 MSA128DOpnd>; 1686 1687class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; 1688class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; 1689class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; 1690class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; 1691 1692class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1693 MSA128BOpnd>; 1694class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1695 MSA128HOpnd>; 1696class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1697 MSA128WOpnd>; 1698class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1699 MSA128DOpnd>; 1700 1701class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; 1702class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; 1703class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; 1704class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; 1705 1706class BMNZ_V_DESC { 1707 dag OutOperandList = (outs MSA128BOpnd:$wd); 1708 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1709 MSA128BOpnd:$wt); 1710 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1711 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1712 MSA128BOpnd:$ws, 1713 MSA128BOpnd:$wd_in))]; 1714 InstrItinClass Itinerary = NoItinerary; 1715 string Constraints = "$wd = $wd_in"; 1716} 1717 1718class BMNZI_B_DESC { 1719 dag OutOperandList = (outs MSA128BOpnd:$wd); 1720 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1721 vsplat_uimm8:$u8); 1722 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1723 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1724 MSA128BOpnd:$ws, 1725 MSA128BOpnd:$wd_in))]; 1726 InstrItinClass Itinerary = NoItinerary; 1727 string Constraints = "$wd = $wd_in"; 1728} 1729 1730class BMZ_V_DESC { 1731 dag OutOperandList = (outs MSA128BOpnd:$wd); 1732 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1733 MSA128BOpnd:$wt); 1734 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1735 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1736 MSA128BOpnd:$wd_in, 1737 MSA128BOpnd:$ws))]; 1738 InstrItinClass Itinerary = NoItinerary; 1739 string Constraints = "$wd = $wd_in"; 1740} 1741 1742class BMZI_B_DESC { 1743 dag OutOperandList = (outs MSA128BOpnd:$wd); 1744 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1745 vsplat_uimm8:$u8); 1746 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1747 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1748 MSA128BOpnd:$wd_in, 1749 MSA128BOpnd:$ws))]; 1750 InstrItinClass Itinerary = NoItinerary; 1751 string Constraints = "$wd = $wd_in"; 1752} 1753 1754class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1755class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1756class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1757class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1758 1759class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1760 MSA128BOpnd>; 1761class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1762 MSA128HOpnd>; 1763class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1764 MSA128WOpnd>; 1765class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1766 MSA128DOpnd>; 1767 1768class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1769class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1770class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1771class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1772 1773class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1774 1775class BSEL_V_DESC { 1776 dag OutOperandList = (outs MSA128BOpnd:$wd); 1777 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1778 MSA128BOpnd:$wt); 1779 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1780 // Note that vselect and BSEL_V treat the condition operand the opposite way 1781 // from each other. 1782 // (vselect cond, if_set, if_clear) 1783 // (BSEL_V cond, if_clear, if_set) 1784 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1785 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1786 MSA128BOpnd:$ws))]; 1787 InstrItinClass Itinerary = NoItinerary; 1788 string Constraints = "$wd = $wd_in"; 1789} 1790 1791class BSELI_B_DESC { 1792 dag OutOperandList = (outs MSA128BOpnd:$wd); 1793 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1794 vsplat_uimm8:$u8); 1795 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1796 // Note that vselect and BSEL_V treat the condition operand the opposite way 1797 // from each other. 1798 // (vselect cond, if_set, if_clear) 1799 // (BSEL_V cond, if_clear, if_set) 1800 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1801 vsplati8_uimm8:$u8, 1802 MSA128BOpnd:$ws))]; 1803 InstrItinClass Itinerary = NoItinerary; 1804 string Constraints = "$wd = $wd_in"; 1805} 1806 1807class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1808class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1809class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1810class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1811 1812class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1813 MSA128BOpnd>; 1814class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1815 MSA128HOpnd>; 1816class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1817 MSA128WOpnd>; 1818class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1819 MSA128DOpnd>; 1820 1821class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1822class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1823class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1824class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1825 1826class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1827 1828class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1829 IsCommutable; 1830class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1831 IsCommutable; 1832class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1833 IsCommutable; 1834class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1835 IsCommutable; 1836 1837class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1838 MSA128BOpnd>; 1839class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1840 MSA128HOpnd>; 1841class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1842 MSA128WOpnd>; 1843class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1844 MSA128DOpnd>; 1845 1846class CFCMSA_DESC { 1847 dag OutOperandList = (outs GPR32Opnd:$rd); 1848 dag InOperandList = (ins MSA128CROpnd:$cs); 1849 string AsmString = "cfcmsa\t$rd, $cs"; 1850 InstrItinClass Itinerary = NoItinerary; 1851 bit hasSideEffects = 1; 1852} 1853 1854class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1855class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1856class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1857class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1858 1859class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1860class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1861class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1862class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1863 1864class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1865 vsplati8_simm5, MSA128BOpnd>; 1866class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1867 vsplati16_simm5, MSA128HOpnd>; 1868class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1869 vsplati32_simm5, MSA128WOpnd>; 1870class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1871 vsplati64_simm5, MSA128DOpnd>; 1872 1873class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1874 vsplati8_uimm5, MSA128BOpnd>; 1875class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1876 vsplati16_uimm5, MSA128HOpnd>; 1877class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1878 vsplati32_uimm5, MSA128WOpnd>; 1879class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1880 vsplati64_uimm5, MSA128DOpnd>; 1881 1882class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1883class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1884class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1885class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1886 1887class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1888class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1889class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1890class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1891 1892class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1893 vsplati8_simm5, MSA128BOpnd>; 1894class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1895 vsplati16_simm5, MSA128HOpnd>; 1896class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1897 vsplati32_simm5, MSA128WOpnd>; 1898class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1899 vsplati64_simm5, MSA128DOpnd>; 1900 1901class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1902 vsplati8_uimm5, MSA128BOpnd>; 1903class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1904 vsplati16_uimm5, MSA128HOpnd>; 1905class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1906 vsplati32_uimm5, MSA128WOpnd>; 1907class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1908 vsplati64_uimm5, MSA128DOpnd>; 1909 1910class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1911 GPR32Opnd, MSA128BOpnd>; 1912class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1913 GPR32Opnd, MSA128HOpnd>; 1914class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1915 GPR32Opnd, MSA128WOpnd>; 1916class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1917 GPR64Opnd, MSA128DOpnd>; 1918 1919class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1920 GPR32Opnd, MSA128BOpnd>; 1921class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1922 GPR32Opnd, MSA128HOpnd>; 1923class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1924 GPR32Opnd, MSA128WOpnd>; 1925class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64, 1926 GPR64Opnd, MSA128DOpnd>; 1927 1928class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32, 1929 MSA128W>; 1930class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64, 1931 MSA128D>; 1932 1933class CTCMSA_DESC { 1934 dag OutOperandList = (outs); 1935 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1936 string AsmString = "ctcmsa\t$cd, $rs"; 1937 InstrItinClass Itinerary = NoItinerary; 1938 bit hasSideEffects = 1; 1939} 1940 1941class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1942class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1943class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1944class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1945 1946class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1947class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1948class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1949class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1950 1951class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1952 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1953 IsCommutable; 1954class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1955 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1956 IsCommutable; 1957class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1958 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1959 IsCommutable; 1960 1961class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1962 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1963 IsCommutable; 1964class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1965 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1966 IsCommutable; 1967class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1968 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1969 IsCommutable; 1970 1971class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1972 MSA128HOpnd, MSA128BOpnd, 1973 MSA128BOpnd>, IsCommutable; 1974class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1975 MSA128WOpnd, MSA128HOpnd, 1976 MSA128HOpnd>, IsCommutable; 1977class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1978 MSA128DOpnd, MSA128WOpnd, 1979 MSA128WOpnd>, IsCommutable; 1980 1981class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1982 MSA128HOpnd, MSA128BOpnd, 1983 MSA128BOpnd>, IsCommutable; 1984class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1985 MSA128WOpnd, MSA128HOpnd, 1986 MSA128HOpnd>, IsCommutable; 1987class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1988 MSA128DOpnd, MSA128WOpnd, 1989 MSA128WOpnd>, IsCommutable; 1990 1991class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1992 MSA128HOpnd, MSA128BOpnd, 1993 MSA128BOpnd>; 1994class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1995 MSA128WOpnd, MSA128HOpnd, 1996 MSA128HOpnd>; 1997class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1998 MSA128DOpnd, MSA128WOpnd, 1999 MSA128WOpnd>; 2000 2001class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 2002 MSA128HOpnd, MSA128BOpnd, 2003 MSA128BOpnd>; 2004class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 2005 MSA128WOpnd, MSA128HOpnd, 2006 MSA128HOpnd>; 2007class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 2008 MSA128DOpnd, MSA128WOpnd, 2009 MSA128WOpnd>; 2010 2011class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 2012 IsCommutable; 2013class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 2014 IsCommutable; 2015 2016class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 2017 IsCommutable; 2018class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 2019 IsCommutable; 2020 2021class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 2022 IsCommutable; 2023class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 2024 IsCommutable; 2025 2026class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 2027 MSA128WOpnd>; 2028class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 2029 MSA128DOpnd>; 2030 2031class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 2032class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 2033 2034class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 2035class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 2036 2037class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 2038 IsCommutable; 2039class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 2040 IsCommutable; 2041 2042class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 2043 IsCommutable; 2044class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 2045 IsCommutable; 2046 2047class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 2048 IsCommutable; 2049class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2050 IsCommutable; 2051 2052class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2053 IsCommutable; 2054class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2055 IsCommutable; 2056 2057class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2058 IsCommutable; 2059class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2060 IsCommutable; 2061 2062class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2063 IsCommutable; 2064class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2065 IsCommutable; 2066 2067class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2068 IsCommutable; 2069class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2070 IsCommutable; 2071 2072class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2073class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2074 2075class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2076 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2077class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2078 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2079 2080// The fexp2.df instruction multiplies the first operand by 2 to the power of 2081// the second operand. We therefore need a pseudo-insn in order to invent the 2082// 1.0 when we only need to match ISD::FEXP2. 2083class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2084class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2085let usesCustomInserter = 1 in { 2086 class FEXP2_W_1_PSEUDO_DESC : 2087 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2088 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2089 class FEXP2_D_1_PSEUDO_DESC : 2090 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2091 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2092} 2093 2094class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2095 MSA128WOpnd, MSA128HOpnd>; 2096class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2097 MSA128DOpnd, MSA128WOpnd>; 2098 2099class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2100 MSA128WOpnd, MSA128HOpnd>; 2101class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2102 MSA128DOpnd, MSA128WOpnd>; 2103 2104class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2105class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2106 2107class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2108class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2109 2110class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2111 MSA128WOpnd, MSA128HOpnd>; 2112class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2113 MSA128DOpnd, MSA128WOpnd>; 2114 2115class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2116 MSA128WOpnd, MSA128HOpnd>; 2117class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2118 MSA128DOpnd, MSA128WOpnd>; 2119 2120class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2121 MSA128BOpnd, GPR32Opnd>; 2122class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2123 MSA128HOpnd, GPR32Opnd>; 2124class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2125 MSA128WOpnd, GPR32Opnd>; 2126class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2127 MSA128DOpnd, GPR64Opnd>; 2128 2129class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2130 FGR32>; 2131class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2132 FGR64>; 2133 2134class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2135class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2136 2137class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2138class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2139 2140class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2141class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2142 2143class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2144 MSA128WOpnd>; 2145class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2146 MSA128DOpnd>; 2147 2148class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2149class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2150 2151class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2152 MSA128WOpnd>; 2153class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2154 MSA128DOpnd>; 2155 2156class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>; 2157class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>; 2158 2159class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2160class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2161 2162class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2163class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2164 2165class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2166class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2167 2168class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2169 MSA128WOpnd>; 2170class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2171 MSA128DOpnd>; 2172 2173class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2174class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2175 2176class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2177class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2178 2179class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2180class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2181 2182class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2183class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2184 2185class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2186class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2187 2188class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2189class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2190 2191class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2192class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2193 2194class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2195class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2196 2197class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2198 MSA128WOpnd>; 2199class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2200 MSA128DOpnd>; 2201 2202class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2203 MSA128WOpnd>; 2204class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2205 MSA128DOpnd>; 2206 2207class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2208 MSA128WOpnd>; 2209class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2210 MSA128DOpnd>; 2211 2212class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2213 MSA128WOpnd>; 2214class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2215 MSA128DOpnd>; 2216 2217class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2218 MSA128WOpnd>; 2219class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2220 MSA128DOpnd>; 2221 2222class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2223 MSA128WOpnd>; 2224class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2225 MSA128DOpnd>; 2226 2227class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2228 MSA128WOpnd>; 2229class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2230 MSA128DOpnd>; 2231 2232class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2233 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2234class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2235 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2236 2237class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2238 MSA128WOpnd>; 2239class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2240 MSA128DOpnd>; 2241 2242class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2243 MSA128WOpnd>; 2244class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2245 MSA128DOpnd>; 2246 2247class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2248 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2249class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2250 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2251class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2252 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2253 2254class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2255 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2256class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2257 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2258class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2259 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2260 2261class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2262 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2263class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2264 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2265class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2266 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2267 2268class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2269 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2270class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2271 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2272class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2273 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2274 2275class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2276class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2277class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2278class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2279 2280class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2281class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2282class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2283class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2284 2285class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2286class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2287class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2288class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2289 2290class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2291class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2292class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2293class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2294 2295class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, 2296 MSA128BOpnd, GPR32Opnd>; 2297class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, 2298 MSA128HOpnd, GPR32Opnd>; 2299class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, 2300 MSA128WOpnd, GPR32Opnd>; 2301class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, 2302 MSA128DOpnd, GPR64Opnd>; 2303 2304class INSERT_B_VIDX_PSEUDO_DESC : 2305 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd>; 2306class INSERT_H_VIDX_PSEUDO_DESC : 2307 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd>; 2308class INSERT_W_VIDX_PSEUDO_DESC : 2309 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd>; 2310class INSERT_D_VIDX_PSEUDO_DESC : 2311 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd>; 2312 2313class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2314 MSA128WOpnd, FGR32Opnd>; 2315class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2316 MSA128DOpnd, FGR64Opnd>; 2317 2318class INSERT_FW_VIDX_PSEUDO_DESC : 2319 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd>; 2320class INSERT_FD_VIDX_PSEUDO_DESC : 2321 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd>; 2322 2323class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, 2324 MSA128BOpnd>; 2325class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, 2326 MSA128HOpnd>; 2327class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, 2328 MSA128WOpnd>; 2329class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, 2330 MSA128DOpnd>; 2331 2332class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2333 ValueType TyNode, RegisterOperand ROWD, 2334 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2335 InstrItinClass itin = NoItinerary> { 2336 dag OutOperandList = (outs ROWD:$wd); 2337 dag InOperandList = (ins MemOpnd:$addr); 2338 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2339 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2340 InstrItinClass Itinerary = itin; 2341 string DecoderMethod = "DecodeMSA128Mem"; 2342} 2343 2344class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; 2345class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; 2346class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; 2347class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; 2348 2349class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2350class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2351class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2352class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2353 2354class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2355 RegisterOperand RORS = RORD, RegisterOperand RORT = RORD, 2356 InstrItinClass itin = NoItinerary > { 2357 dag OutOperandList = (outs RORD:$rd); 2358 dag InOperandList = (ins RORS:$rs, RORT:$rt, LSAImm:$sa); 2359 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2360 list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt, 2361 (shl RORS:$rs, 2362 immZExt2Lsa:$sa)))]; 2363 InstrItinClass Itinerary = itin; 2364} 2365 2366class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>; 2367class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>; 2368 2369class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2370 MSA128HOpnd>; 2371class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2372 MSA128WOpnd>; 2373 2374class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2375 MSA128HOpnd>; 2376class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2377 MSA128WOpnd>; 2378 2379class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2380class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2381class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2382class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2383 2384class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2385class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2386class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2387class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2388 2389class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; 2390class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; 2391class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; 2392class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; 2393 2394class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; 2395class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; 2396class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; 2397class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; 2398 2399class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, 2400 MSA128BOpnd>; 2401class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, 2402 MSA128HOpnd>; 2403class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, 2404 MSA128WOpnd>; 2405class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, 2406 MSA128DOpnd>; 2407 2408class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, 2409 MSA128BOpnd>; 2410class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, 2411 MSA128HOpnd>; 2412class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, 2413 MSA128WOpnd>; 2414class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, 2415 MSA128DOpnd>; 2416 2417class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2418class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2419class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2420class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2421 2422class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; 2423class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; 2424class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; 2425class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; 2426 2427class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; 2428class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; 2429class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; 2430class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; 2431 2432class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, 2433 MSA128BOpnd>; 2434class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, 2435 MSA128HOpnd>; 2436class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, 2437 MSA128WOpnd>; 2438class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, 2439 MSA128DOpnd>; 2440 2441class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, 2442 MSA128BOpnd>; 2443class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, 2444 MSA128HOpnd>; 2445class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, 2446 MSA128WOpnd>; 2447class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, 2448 MSA128DOpnd>; 2449 2450class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2451class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2452class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2453class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2454 2455class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2456class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2457class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2458class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2459 2460class MOVE_V_DESC { 2461 dag OutOperandList = (outs MSA128BOpnd:$wd); 2462 dag InOperandList = (ins MSA128BOpnd:$ws); 2463 string AsmString = "move.v\t$wd, $ws"; 2464 list<dag> Pattern = []; 2465 InstrItinClass Itinerary = NoItinerary; 2466} 2467 2468class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2469 MSA128HOpnd>; 2470class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2471 MSA128WOpnd>; 2472 2473class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2474 MSA128HOpnd>; 2475class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2476 MSA128WOpnd>; 2477 2478class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2479class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2480class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2481class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2482 2483class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2484 MSA128HOpnd>; 2485class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2486 MSA128WOpnd>; 2487 2488class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2489 MSA128HOpnd>; 2490class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2491 MSA128WOpnd>; 2492 2493class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2494class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2495class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2496class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2497 2498class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2499class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2500class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2501class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2502 2503class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2504class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2505class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2506class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2507 2508class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2509class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2510class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2511class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2512 2513class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2514 MSA128BOpnd>; 2515 2516class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2517class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2518class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2519class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2520 2521class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2522 2523class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2524class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2525class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2526class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2527 2528class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2529class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2530class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2531class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2532 2533class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2534class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2535class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2536class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2537 2538class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, 2539 MSA128BOpnd>; 2540class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, 2541 MSA128HOpnd>; 2542class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, 2543 MSA128WOpnd>; 2544class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, 2545 MSA128DOpnd>; 2546 2547class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, 2548 MSA128BOpnd>; 2549class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, 2550 MSA128HOpnd>; 2551class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, 2552 MSA128WOpnd>; 2553class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, 2554 MSA128DOpnd>; 2555 2556class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2557class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2558class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2559 2560class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2561class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2562class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2563class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2564 2565class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2566 MSA128BOpnd>; 2567class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2568 MSA128HOpnd>; 2569class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2570 MSA128WOpnd>; 2571class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2572 MSA128DOpnd>; 2573 2574class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2575class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2576class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2577class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2578 2579class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2580 MSA128BOpnd>; 2581class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2582 MSA128HOpnd>; 2583class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2584 MSA128WOpnd>; 2585class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2586 MSA128DOpnd>; 2587 2588class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2589 MSA128BOpnd>; 2590class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2591 MSA128HOpnd>; 2592class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2593 MSA128WOpnd>; 2594class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2595 MSA128DOpnd>; 2596 2597class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2598 MSA128BOpnd>; 2599class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2600 MSA128HOpnd>; 2601class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2602 MSA128WOpnd>; 2603class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2604 MSA128DOpnd>; 2605 2606class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2607class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2608class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2609class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2610 2611class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2612 MSA128BOpnd>; 2613class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2614 MSA128HOpnd>; 2615class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2616 MSA128WOpnd>; 2617class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2618 MSA128DOpnd>; 2619 2620class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2621class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2622class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2623class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2624 2625class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b, 2626 MSA128BOpnd>; 2627class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h, 2628 MSA128HOpnd>; 2629class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w, 2630 MSA128WOpnd>; 2631class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d, 2632 MSA128DOpnd>; 2633 2634class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2635class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2636class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2637class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2638 2639class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2640 MSA128BOpnd>; 2641class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2642 MSA128HOpnd>; 2643class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2644 MSA128WOpnd>; 2645class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2646 MSA128DOpnd>; 2647 2648class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2649class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2650class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2651class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2652 2653class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b, 2654 MSA128BOpnd>; 2655class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h, 2656 MSA128HOpnd>; 2657class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w, 2658 MSA128WOpnd>; 2659class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, 2660 MSA128DOpnd>; 2661 2662class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2663 ValueType TyNode, RegisterOperand ROWD, 2664 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, 2665 InstrItinClass itin = NoItinerary> { 2666 dag OutOperandList = (outs); 2667 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2668 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2669 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2670 InstrItinClass Itinerary = itin; 2671 string DecoderMethod = "DecodeMSA128Mem"; 2672} 2673 2674class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; 2675class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; 2676class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; 2677class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; 2678 2679class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2680 MSA128BOpnd>; 2681class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2682 MSA128HOpnd>; 2683class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2684 MSA128WOpnd>; 2685class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2686 MSA128DOpnd>; 2687 2688class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2689 MSA128BOpnd>; 2690class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2691 MSA128HOpnd>; 2692class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2693 MSA128WOpnd>; 2694class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2695 MSA128DOpnd>; 2696 2697class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2698 MSA128BOpnd>; 2699class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2700 MSA128HOpnd>; 2701class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2702 MSA128WOpnd>; 2703class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2704 MSA128DOpnd>; 2705 2706class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2707 MSA128BOpnd>; 2708class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2709 MSA128HOpnd>; 2710class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2711 MSA128WOpnd>; 2712class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2713 MSA128DOpnd>; 2714 2715class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2716class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2717class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2718class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2719 2720class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2721 MSA128BOpnd>; 2722class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2723 MSA128HOpnd>; 2724class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2725 MSA128WOpnd>; 2726class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2727 MSA128DOpnd>; 2728 2729class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2730class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2731class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2732class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2733 2734class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2735class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2736class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2737class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2738 2739class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2740 MSA128BOpnd>; 2741 2742// Instruction defs. 2743def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2744def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2745def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2746def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2747 2748def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2749def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2750def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2751def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2752 2753def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2754def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2755def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2756def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2757 2758def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2759def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2760def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2761def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2762 2763def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2764def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2765def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2766def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2767 2768def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2769def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2770def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2771def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2772 2773def AND_V : AND_V_ENC, AND_V_DESC; 2774def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2775 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2776 MSA128BOpnd:$ws, 2777 MSA128BOpnd:$wt)>; 2778def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2779 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2780 MSA128BOpnd:$ws, 2781 MSA128BOpnd:$wt)>; 2782def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2783 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2784 MSA128BOpnd:$ws, 2785 MSA128BOpnd:$wt)>; 2786 2787def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2788 2789def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2790def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2791def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2792def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2793 2794def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2795def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2796def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2797def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2798 2799def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2800def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2801def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2802def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2803 2804def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2805def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2806def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2807def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2808 2809def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2810def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2811def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2812def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2813 2814def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2815def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2816def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2817def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2818 2819def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2820def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2821def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2822def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2823 2824def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2825def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2826def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2827def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2828 2829def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2830def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2831def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2832def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2833 2834def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2835def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2836def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2837def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2838 2839def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2840def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2841def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2842def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2843 2844def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2845def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2846def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2847def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2848 2849def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2850 2851def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2852 2853def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2854 2855def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2856 2857def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2858def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2859def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2860def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2861 2862def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2863def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2864def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2865def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2866 2867def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2868def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2869def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2870def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2871 2872def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2873 2874def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2875 2876class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2877 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2878 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2879 // Note that vselect and BSEL_V treat the condition operand the opposite way 2880 // from each other. 2881 // (vselect cond, if_set, if_clear) 2882 // (BSEL_V cond, if_clear, if_set) 2883 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2884 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2885 let Constraints = "$wd_in = $wd"; 2886} 2887 2888def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2889def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2890def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2891def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2892def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2893 2894def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2895 2896def BSET_B : BSET_B_ENC, BSET_B_DESC; 2897def BSET_H : BSET_H_ENC, BSET_H_DESC; 2898def BSET_W : BSET_W_ENC, BSET_W_DESC; 2899def BSET_D : BSET_D_ENC, BSET_D_DESC; 2900 2901def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2902def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2903def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2904def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2905 2906def BZ_B : BZ_B_ENC, BZ_B_DESC; 2907def BZ_H : BZ_H_ENC, BZ_H_DESC; 2908def BZ_W : BZ_W_ENC, BZ_W_DESC; 2909def BZ_D : BZ_D_ENC, BZ_D_DESC; 2910 2911def BZ_V : BZ_V_ENC, BZ_V_DESC; 2912 2913def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2914def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2915def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2916def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2917 2918def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2919def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2920def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2921def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2922 2923def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2924 2925def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2926def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2927def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2928def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2929 2930def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2931def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2932def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2933def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2934 2935def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2936def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2937def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2938def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2939 2940def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2941def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2942def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2943def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2944 2945def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2946def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2947def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2948def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2949 2950def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2951def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2952def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2953def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2954 2955def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2956def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2957def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2958def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2959 2960def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2961def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2962def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2963def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2964 2965def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2966def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2967def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2968def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC; 2969 2970def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2971def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2972def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC; 2973def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC; 2974 2975def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2976def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2977 2978def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2979 2980def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2981def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2982def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2983def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2984 2985def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2986def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2987def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2988def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2989 2990def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2991def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2992def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2993 2994def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2995def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2996def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2997 2998def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2999def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 3000def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 3001 3002def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 3003def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 3004def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 3005 3006def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 3007def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 3008def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 3009 3010def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 3011def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 3012def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 3013 3014def FADD_W : FADD_W_ENC, FADD_W_DESC; 3015def FADD_D : FADD_D_ENC, FADD_D_DESC; 3016 3017def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 3018def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 3019 3020def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 3021def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 3022 3023def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 3024def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3025 3026def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3027def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3028 3029def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3030def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3031 3032def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3033def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3034 3035def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3036def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3037 3038def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3039def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3040 3041def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3042def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3043 3044def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3045def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3046 3047def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3048def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3049 3050def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3051def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3052 3053def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3054def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3055 3056def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3057def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3058 3059def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3060def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3061def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3062def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3063 3064def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3065def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3066 3067def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3068def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3069 3070def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3071def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3072 3073def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3074def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3075 3076def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3077def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3078 3079def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3080def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3081 3082def FILL_B : FILL_B_ENC, FILL_B_DESC; 3083def FILL_H : FILL_H_ENC, FILL_H_DESC; 3084def FILL_W : FILL_W_ENC, FILL_W_DESC; 3085def FILL_D : FILL_D_ENC, FILL_D_DESC; 3086def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3087def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3088 3089def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3090def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3091 3092def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3093def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3094 3095def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3096def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3097 3098def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3099def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3100 3101def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3102def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3103 3104def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3105def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3106 3107def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3108def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3109 3110def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3111def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3112 3113def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3114def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3115 3116def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3117def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3118 3119def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3120def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3121 3122def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3123def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3124 3125def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3126def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3127 3128def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3129def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3130 3131def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3132def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3133 3134def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3135def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3136 3137def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3138def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3139 3140def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3141def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3142 3143def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3144def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3145 3146def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3147def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3148 3149def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3150def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3151 3152def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3153def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3154 3155def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3156def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3157 3158def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3159def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3160 3161def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3162def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3163 3164def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3165def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3166 3167def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3168def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3169 3170def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3171def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3172 3173def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3174def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3175 3176def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3177def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3178def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3179 3180def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3181def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3182def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3183 3184def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3185def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3186def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3187 3188def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3189def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3190def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3191 3192def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3193def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3194def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3195def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3196 3197def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3198def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3199def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3200def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3201 3202def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3203def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3204def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3205def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3206 3207def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3208def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3209def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3210def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3211 3212def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3213def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3214def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3215def INSERT_D : INSERT_D_ENC, INSERT_D_DESC; 3216 3217// INSERT_FW_PSEUDO defined after INSVE_W 3218// INSERT_FD_PSEUDO defined after INSVE_D 3219 3220// There is a fourth operand that is not present in the encoding. Use a 3221// custom decoder to get a chance to add it. 3222let DecoderMethod = "DecodeINSVE_DF" in { 3223 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3224 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3225 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3226 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3227} 3228 3229def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3230def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3231 3232def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3233def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3234def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3235def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3236def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3237def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3238 3239def LD_B: LD_B_ENC, LD_B_DESC; 3240def LD_H: LD_H_ENC, LD_H_DESC; 3241def LD_W: LD_W_ENC, LD_W_DESC; 3242def LD_D: LD_D_ENC, LD_D_DESC; 3243 3244def LDI_B : LDI_B_ENC, LDI_B_DESC; 3245def LDI_H : LDI_H_ENC, LDI_H_DESC; 3246def LDI_W : LDI_W_ENC, LDI_W_DESC; 3247def LDI_D : LDI_D_ENC, LDI_D_DESC; 3248 3249def LSA : LSA_ENC, LSA_DESC; 3250def DLSA : DLSA_ENC, DLSA_DESC; 3251 3252def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3253def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3254 3255def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3256def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3257 3258def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3259def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3260def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3261def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3262 3263def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3264def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3265def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3266def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3267 3268def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3269def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3270def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3271def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3272 3273def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3274def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3275def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3276def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3277 3278def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3279def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3280def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3281def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3282 3283def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3284def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3285def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3286def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3287 3288def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3289def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3290def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3291def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3292 3293def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3294def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3295def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3296def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3297 3298def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3299def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3300def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3301def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3302 3303def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3304def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3305def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3306def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3307 3308def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3309def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3310def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3311def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3312 3313def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3314def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3315def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3316def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3317 3318def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3319def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3320def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3321def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3322 3323def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3324 3325def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3326def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3327 3328def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3329def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3330 3331def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3332def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3333def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3334def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3335 3336def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3337def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3338 3339def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3340def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3341 3342def MULV_B : MULV_B_ENC, MULV_B_DESC; 3343def MULV_H : MULV_H_ENC, MULV_H_DESC; 3344def MULV_W : MULV_W_ENC, MULV_W_DESC; 3345def MULV_D : MULV_D_ENC, MULV_D_DESC; 3346 3347def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3348def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3349def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3350def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3351 3352def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3353def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3354def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3355def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3356 3357def NOR_V : NOR_V_ENC, NOR_V_DESC; 3358def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3359 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3360 MSA128BOpnd:$ws, 3361 MSA128BOpnd:$wt)>; 3362def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3363 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3364 MSA128BOpnd:$ws, 3365 MSA128BOpnd:$wt)>; 3366def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3367 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3368 MSA128BOpnd:$ws, 3369 MSA128BOpnd:$wt)>; 3370 3371def NORI_B : NORI_B_ENC, NORI_B_DESC; 3372 3373def OR_V : OR_V_ENC, OR_V_DESC; 3374def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3375 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3376 MSA128BOpnd:$ws, 3377 MSA128BOpnd:$wt)>; 3378def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3379 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3380 MSA128BOpnd:$ws, 3381 MSA128BOpnd:$wt)>; 3382def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3383 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3384 MSA128BOpnd:$ws, 3385 MSA128BOpnd:$wt)>; 3386 3387def ORI_B : ORI_B_ENC, ORI_B_DESC; 3388 3389def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3390def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3391def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3392def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3393 3394def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3395def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3396def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3397def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3398 3399def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3400def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3401def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3402def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3403 3404def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3405def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3406def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3407def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3408 3409def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3410def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3411def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3412def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3413 3414def SHF_B : SHF_B_ENC, SHF_B_DESC; 3415def SHF_H : SHF_H_ENC, SHF_H_DESC; 3416def SHF_W : SHF_W_ENC, SHF_W_DESC; 3417 3418def SLD_B : SLD_B_ENC, SLD_B_DESC; 3419def SLD_H : SLD_H_ENC, SLD_H_DESC; 3420def SLD_W : SLD_W_ENC, SLD_W_DESC; 3421def SLD_D : SLD_D_ENC, SLD_D_DESC; 3422 3423def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3424def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3425def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3426def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3427 3428def SLL_B : SLL_B_ENC, SLL_B_DESC; 3429def SLL_H : SLL_H_ENC, SLL_H_DESC; 3430def SLL_W : SLL_W_ENC, SLL_W_DESC; 3431def SLL_D : SLL_D_ENC, SLL_D_DESC; 3432 3433def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3434def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3435def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3436def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3437 3438def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3439def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3440def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3441def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3442 3443def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3444def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3445def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3446def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3447 3448def SRA_B : SRA_B_ENC, SRA_B_DESC; 3449def SRA_H : SRA_H_ENC, SRA_H_DESC; 3450def SRA_W : SRA_W_ENC, SRA_W_DESC; 3451def SRA_D : SRA_D_ENC, SRA_D_DESC; 3452 3453def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3454def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3455def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3456def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3457 3458def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3459def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3460def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3461def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3462 3463def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3464def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3465def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3466def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3467 3468def SRL_B : SRL_B_ENC, SRL_B_DESC; 3469def SRL_H : SRL_H_ENC, SRL_H_DESC; 3470def SRL_W : SRL_W_ENC, SRL_W_DESC; 3471def SRL_D : SRL_D_ENC, SRL_D_DESC; 3472 3473def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3474def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3475def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3476def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3477 3478def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3479def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3480def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3481def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3482 3483def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3484def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3485def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3486def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3487 3488def ST_B: ST_B_ENC, ST_B_DESC; 3489def ST_H: ST_H_ENC, ST_H_DESC; 3490def ST_W: ST_W_ENC, ST_W_DESC; 3491def ST_D: ST_D_ENC, ST_D_DESC; 3492 3493def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3494def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3495def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3496def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3497 3498def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3499def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3500def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3501def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3502 3503def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3504def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3505def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3506def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3507 3508def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3509def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3510def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3511def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3512 3513def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3514def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3515def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3516def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3517 3518def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3519def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3520def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3521def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3522 3523def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3524def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3525def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3526def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3527 3528def XOR_V : XOR_V_ENC, XOR_V_DESC; 3529def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3530 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3531 MSA128BOpnd:$ws, 3532 MSA128BOpnd:$wt)>; 3533def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3534 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3535 MSA128BOpnd:$ws, 3536 MSA128BOpnd:$wt)>; 3537def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3538 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3539 MSA128BOpnd:$ws, 3540 MSA128BOpnd:$wt)>; 3541 3542def XORI_B : XORI_B_ENC, XORI_B_DESC; 3543 3544// Patterns. 3545class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3546 Pat<pattern, result>, Requires<pred>; 3547 3548def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3549 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3550 3551def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; 3552def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; 3553def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; 3554 3555def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), 3556 (ST_H MSA128H:$ws, addrimm10:$addr)>; 3557def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), 3558 (ST_W MSA128W:$ws, addrimm10:$addr)>; 3559def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), 3560 (ST_D MSA128D:$ws, addrimm10:$addr)>; 3561 3562class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3563 RegisterOperand ROWS = ROWD, 3564 InstrItinClass itin = NoItinerary> : 3565 MSAPseudo<(outs ROWD:$wd), 3566 (ins ROWS:$ws), 3567 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3568 InstrItinClass Itinerary = itin; 3569} 3570def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3571 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3572 MSA128WOpnd:$ws)>; 3573def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3574 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3575 MSA128DOpnd:$ws)>; 3576 3577class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3578 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3579 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3580 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3581 3582// These are endian-independent because the element size doesnt change 3583def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3584def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3585def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3586def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3587def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3588def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3589 3590// Little endian bitcasts are always no-ops 3591def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3592def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3593def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3594def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3595def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3596def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3597 3598def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3599def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3600def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3601def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3602def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3603 3604def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3605def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3606def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3607def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3608def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3609 3610def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3611def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3612def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3613def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3614def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3615 3616def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3617def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3618def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3619def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3620def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3621 3622def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3623def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3624def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3625def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3626def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3627 3628// Big endian bitcasts expand to shuffle instructions. 3629// This is because bitcast is defined to be a store/load sequence and the 3630// vector store/load instructions are mixed-endian with respect to the vector 3631// as a whole (little endian with respect to element order, but big endian 3632// elements). 3633 3634class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3635 RegisterClass DstRC, MSAInst Insn, 3636 RegisterClass ViaRC> : 3637 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3638 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3639 DstRC), 3640 [HasMSA, IsBE]>; 3641 3642class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3643 RegisterClass DstRC, MSAInst Insn, 3644 RegisterClass ViaRC> : 3645 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3646 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3647 DstRC), 3648 [HasMSA, IsBE]>; 3649 3650class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3651 RegisterClass DstRC> : 3652 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3653 3654class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3655 RegisterClass DstRC> : 3656 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3657 3658class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3659 RegisterClass DstRC> : 3660 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3661 (COPY_TO_REGCLASS 3662 (SHF_W 3663 (COPY_TO_REGCLASS 3664 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3665 MSA128W), 177), 3666 DstRC), 3667 [HasMSA, IsBE]>; 3668 3669class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3670 RegisterClass DstRC> : 3671 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3672 3673class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3674 RegisterClass DstRC> : 3675 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3676 3677class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3678 RegisterClass DstRC> : 3679 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3680 3681def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3682def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3683def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3684def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3685def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3686def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3687 3688def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3689def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3690def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3691def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3692def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3693 3694def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3695def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3696def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3697def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3698def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3699 3700def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3701def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3702def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3703def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3704def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3705 3706def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3707def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3708def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3709def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3710def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3711 3712def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3713def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3714def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3715def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3716def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3717 3718def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3719def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3720def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3721def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3722def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3723 3724// Pseudos used to implement BNZ.df, and BZ.df 3725 3726class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3727 RegisterClass RCWS, 3728 InstrItinClass itin = NoItinerary> : 3729 MipsPseudo<(outs GPR32:$dst), 3730 (ins RCWS:$ws), 3731 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3732 bit usesCustomInserter = 1; 3733} 3734 3735def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3736 MSA128B, NoItinerary>; 3737def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3738 MSA128H, NoItinerary>; 3739def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3740 MSA128W, NoItinerary>; 3741def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3742 MSA128D, NoItinerary>; 3743def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3744 MSA128B, NoItinerary>; 3745 3746def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3747 MSA128B, NoItinerary>; 3748def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3749 MSA128H, NoItinerary>; 3750def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3751 MSA128W, NoItinerary>; 3752def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3753 MSA128D, NoItinerary>; 3754def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3755 MSA128B, NoItinerary>; 3756 3757// Vector extraction with variable index 3758def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3759 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3760 i32:$idx), 3761 sub_lo)), 3762 GPR32), (i32 24))>; 3763def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3764 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3765 i32:$idx), 3766 sub_lo)), 3767 GPR32), (i32 16))>; 3768def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3769 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3770 i32:$idx), 3771 sub_lo)), 3772 GPR32)>; 3773def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3774 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3775 i32:$idx), 3776 sub_64)), 3777 GPR64), [HasMSA, IsGP64bit]>; 3778 3779def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3780 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3781 i32:$idx), 3782 sub_lo)), 3783 GPR32), (i32 24))>; 3784def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3785 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3786 i32:$idx), 3787 sub_lo)), 3788 GPR32), (i32 16))>; 3789def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3790 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3791 i32:$idx), 3792 sub_lo)), 3793 GPR32)>; 3794def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3795 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3796 i32:$idx), 3797 sub_64)), 3798 GPR64), [HasMSA, IsGP64bit]>; 3799 3800def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3801 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3802 i32:$idx), 3803 sub_lo))>; 3804def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3805 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3806 i32:$idx), 3807 sub_64))>; 3808