| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 757 EXTLOAD, enumerator
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| D | BasicTTIImpl.h | 511 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT); in getMemoryOpCost()
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| D | SelectionDAGNodes.h | 2103 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZOperators.td | 230 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
245 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
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| D | SystemZISelLowering.cpp | 231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
287 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in SystemZTargetLowering()
2462 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(), in lowerATOMIC_LOAD()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SITargetLowering()
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| D | AMDGPUISelLowering.cpp | 222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
260 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
1431 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
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| D | R600ISelLowering.cpp | 134 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
135 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
1566 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
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| D | AMDGPUInstructions.td | 189 L->getExtensionType() == ISD::EXTLOAD;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
1093 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) { in LegalizeLoadOps()
1121 assert(ExtType != ISD::EXTLOAD && in LegalizeLoadOps()
1125 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, in LegalizeLoadOps()
1452 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(), in ExpandExtractFromVectorThroughStack()
1814 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, in EmitStackConvert()
[all …]
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| D | LegalizeVectorOps.cpp | 528 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, in ExpandLoad()
579 case ISD::EXTLOAD: in ExpandLoad()
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| D | SelectionDAGDumper.cpp | 469 case ISD::EXTLOAD: OS << ", anyext"; break; in print_details()
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| D | DAGCombiner.cpp | 912 : ISD::EXTLOAD) in PromoteOperand()
1134 : ISD::EXTLOAD) in PromoteLoad()
2945 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; in visitAND()
2954 if (Load->getExtensionType() == ISD::EXTLOAD) { in visitAND()
6132 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { in visitANY_EXTEND()
6139 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitANY_EXTEND()
8185 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) { in visitFP_EXTEND()
8187 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, in visitFP_EXTEND()
10505 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy)) in MergeConsecutiveStores()
10951 : ISD::EXTLOAD; in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
[all …]
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| D | LegalizeIntegerTypes.cpp | 457 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); in PromoteIntRes_LOAD()
1929 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
2896 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), in ExpandIntOp_UINT_TO_FP()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
473 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
985 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
991 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), in LowerATOMIC_LOAD()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
227 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in MipsTargetLowering()
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in MipsTargetLowering()
235 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); in MipsTargetLowering()
399 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
2181 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 153 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1317 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType) j, VT, Expand); in HexagonTargetLowering()
1613 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1619 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
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| D | HexagonISelDAGToDAG.cpp | 375 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in NVPTXTargetLowering()
207 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in NVPTXTargetLowering()
208 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in NVPTXTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
601 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
666 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT.getSimpleVT(), Expand); in addTypeForNEON()
2196 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in X86TargetLowering()
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in X86TargetLowering()
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand); in X86TargetLowering()
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
753 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom); in X86TargetLowering()
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom); in X86TargetLowering()
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1382 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1383 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in PPCTargetLowering()
640 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
4754 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, in LowerCall_64SVR4()
5303 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, in LowerCall_Darwin()
5718 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain, in LowerLOAD()
7431 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD, in LowerVectorLoad()
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