| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 499 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 599 ISD = ISD::FCEIL; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 288 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
339 Opcode = ISD::FCEIL; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
456 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
752 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
757 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 154 case ISD::FCEIL: return "fceil"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 74 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
890 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
1735 case ISD::FCEIL: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 311 case ISD::FCEIL: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 77 case ISD::FCEIL: in ScalarizeVectorResult()
618 case ISD::FCEIL: in SplitVectorResult()
1800 case ISD::FCEIL: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3363 case ISD::FCEIL: in ExpandNode()
4242 case ISD::FCEIL: in PromoteNode()
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| D | SelectionDAG.cpp | 2795 case ISD::FCEIL: { in getNode()
2860 case ISD::FCEIL: in getNode()
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| D | SelectionDAGBuilder.cpp | 5000 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in visitIntrinsicCall()
6030 if (visitUnaryFloatCall(I, ISD::FCEIL)) in visitCall()
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| D | DAGCombiner.cpp | 1368 case ISD::FCEIL: return visitFCEIL(N); in visit()
8208 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); in visitFCEIL()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 121 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
245 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
364 setOperationAction(ISD::FCEIL, VT, Expand); in AMDGPUTargetLowering()
612 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
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| D | SIISelLowering.cpp | 202 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in SITargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 297 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in AArch64TargetLowering()
337 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); in AArch64TargetLowering()
367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
401 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
522 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
609 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
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| D | AArch64ISelDAGToDAG.cpp | 2020 case ISD::FCEIL: { in SelectLIBM()
3074 case ISD::FCEIL: in Select()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 842 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 475 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
492 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
509 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
613 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
907 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
914 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 410 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 645 setOperationAction(ISD::FCEIL, MVT::f80, Expand); in X86TargetLowering()
698 setOperationAction(ISD::FCEIL, VT, Expand); in X86TargetLowering()
943 setOperationAction(ISD::FCEIL, RoundedTy, Legal); in X86TargetLowering()
1040 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); in X86TargetLowering()
1053 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in X86TargetLowering()
1323 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal); in X86TargetLowering()
1324 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal); in X86TargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 266 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
|