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Searched refs:FPR (Results 1 – 25 of 29) sorted by relevance

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/external/elfutils/src/backends/
Ds390_corenote.c66 #define FPR(at, n, dwreg) \ macro
71 FPR (1 + 0, 1, 16), /* f0 */
72 FPR (1 + 1, 1, 20), /* f1 */
73 FPR (1 + 2, 1, 17), /* f2 */
74 FPR (1 + 3, 1, 21), /* f3 */
75 FPR (1 + 4, 1, 18), /* f4 */
76 FPR (1 + 5, 1, 22), /* f5 */
77 FPR (1 + 6, 1, 19), /* f6 */
78 FPR (1 + 7, 1, 23), /* f7 */
79 FPR (1 + 8, 1, 24), /* f8 */
[all …]
/external/valgrind/VEX/priv/
Dhost_s390_defs.c3193 s390_disasm(ENC3(MNM, FPR, FPR), "ldr", r1, r2); in s390_emit_LDR()
3203 s390_disasm(ENC3(MNM, FPR, UDXB), "le", r1, d2, x2, b2); in s390_emit_LE()
3213 s390_disasm(ENC3(MNM, FPR, UDXB), "ld", r1, d2, x2, b2); in s390_emit_LD()
3223 s390_disasm(ENC3(MNM, FPR, SDXB), "ley", r1, dh2, dl2, x2, b2); in s390_emit_LEY()
3233 s390_disasm(ENC3(MNM, FPR, SDXB), "ldy", r1, dh2, dl2, x2, b2); in s390_emit_LDY()
3255 s390_disasm(ENC3(MNM, FPR, GPR), "ldgr", r1, r2); in s390_emit_LDGR()
3267 s390_disasm(ENC3(MNM, GPR, FPR), "lgdr", r1, r2); in s390_emit_LGDR()
3277 s390_disasm(ENC2(MNM, FPR), "lzer", r1); in s390_emit_LZER()
3287 s390_disasm(ENC2(MNM, FPR), "lzdr", r1); in s390_emit_LZDR()
3307 s390_disasm(ENC3(MNM, FPR, UDXB), "ste", r1, d2, x2, b2); in s390_emit_STE()
[all …]
Dhost_ppc_defs.h52 #define FPR(_mode64, _enc, _ix64, _ix32) \ macro
90 ST_IN HReg hregPPC_FPR14 ( Bool mode64 ) { return FPR(mode64, 14, 23, 25); } in hregPPC_FPR14()
91 ST_IN HReg hregPPC_FPR15 ( Bool mode64 ) { return FPR(mode64, 15, 24, 26); } in hregPPC_FPR15()
92 ST_IN HReg hregPPC_FPR16 ( Bool mode64 ) { return FPR(mode64, 16, 25, 27); } in hregPPC_FPR16()
93 ST_IN HReg hregPPC_FPR17 ( Bool mode64 ) { return FPR(mode64, 17, 26, 28); } in hregPPC_FPR17()
94 ST_IN HReg hregPPC_FPR18 ( Bool mode64 ) { return FPR(mode64, 18, 27, 29); } in hregPPC_FPR18()
95 ST_IN HReg hregPPC_FPR19 ( Bool mode64 ) { return FPR(mode64, 19, 28, 30); } in hregPPC_FPR19()
96 ST_IN HReg hregPPC_FPR20 ( Bool mode64 ) { return FPR(mode64, 20, 29, 31); } in hregPPC_FPR20()
97 ST_IN HReg hregPPC_FPR21 ( Bool mode64 ) { return FPR(mode64, 21, 30, 32); } in hregPPC_FPR21()
116 #undef FPR
Dguest_s390_toIR.c1961 s390_disasm(ENC3(MNM, FPR, FPR), mnm, r1, r2); in s390_format_RR_FF()
1988 s390_disasm(ENC3(MNM, FPR, FPR), mnm, r1, r2); in s390_format_RRE_FF()
1998 s390_disasm(ENC3(MNM, GPR, FPR), mnm, r1, r2); in s390_format_RRE_RF()
2008 s390_disasm(ENC3(MNM, FPR, GPR), mnm, r1, r2); in s390_format_RRE_FR()
2028 s390_disasm(ENC2(MNM, FPR), mnm, r1); in s390_format_RRE_F0()
2048 s390_disasm(ENC4(MNM, FPR, FPR, FPR), mnm, r1, r3, r2); in s390_format_RRF_F0FF()
2058 s390_disasm(ENC4(MNM, FPR, FPR, GPR), mnm, r1, r3, r2); in s390_format_RRF_F0FR()
2069 s390_disasm(ENC5(MNM, FPR, UINT, FPR, UINT), mnm, r1, m3, r2, m4); in s390_format_RRF_UUFF()
2079 s390_disasm(ENC4(MNM, FPR, FPR, UINT), mnm, r1, r2, m4); in s390_format_RRF_0UFF()
2090 s390_disasm(ENC5(MNM, FPR, UINT, GPR, UINT), mnm, r1, m3, r2, m4); in s390_format_RRF_UUFR()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZMachineFunctionInfo.h51 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
DSystemZRegisterInfo.td122 // Maps FPR register numbers to their DWARF encoding.
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td47 // FPR - One of the 32 64-bit floating-point registers
48 class FPR<bits<5> num, string n> : PPCReg<n> {
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
115 def F#Index : FPR<Index, "f"#Index>,
126 def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,
138 def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
139 DwarfRegAlias<!cast<FPR>("F"#Index)>;
DPPCScheduleP8.td251 // to either the LU (GPR store) or the VSU (FPR store).
/external/lldb/source/Plugins/Process/POSIX/
DRegisterContext_x86_64.h303 struct FPR struct
329 … FPR m_fpr; // floating-point registers including extended register sets.
DRegisterContext_x86_64.cpp294 (offsetof(RegisterContext_x86_64::FPR, xstate) + \
355 #define REG_CONTEXT_SIZE (GetGPRSize() + sizeof(RegisterContext_x86_64::FPR))
501 ::memset(&m_fpr, 0, sizeof(RegisterContext_x86_64::FPR)); in RegisterContext_x86_64()
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td51 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
167 [!cast<FPR>("F"#!shl(I, 1)),
168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
/external/llvm/test/CodeGen/AArch64/
Darm64-fixed-point-scalar-cvt-dagcombine.ll5 ; of the value to a GPR and back to and FPR.
/external/llvm/test/CodeGen/SystemZ/
Dasm-10.ll1 ; Test the FPR constraint "f".
Dframe-04.ll68 ; Like f1, but requires one fewer FPR pair. We allocate in numerical order,
121 ; Like f1, but requires only one call-saved FPR pair. We allocate in
Dargs-02.ll1 ; Test the handling of GPR, FPR and stack arguments when integers are
Dargs-03.ll1 ; Test the handling of GPR, FPR and stack arguments when integers are
Dargs-01.ll1 ; Test the handling of GPR, FPR and stack arguments when no extension
Dframe-02.ll91 ; Like f1, but requires one fewer FPR. We allocate in numerical order,
170 ; Like f1, but should require only one call-saved FPR.
Dframe-03.ll93 ; Like f1, but requires one fewer FPR. We allocate in numerical order,
172 ; Like f1, but should require only one call-saved FPR.
Dargs-04.ll1 ; Test incoming GPR, FPR and stack arguments when no extension type is given.
Dfp-move-02.ll12 ; 32 bits of the FPR.
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
Dframe-07.ll9 ; as well as the 8 FPR save slots. Get a frame of size 4128 by allocating
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td46 // up to eight each of GPR and FPR.
127 // up to eight each of GPR and FPR.
DAArch64InstrInfo.td1878 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1880 def : Pat<(store (VecTy FPR:$Rt),
1882 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1884 def : Pat<(store (VecTy FPR:$Rt),
1886 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
4628 // SCVTF GPR -> FPR is 9 cycles.
4629 // SCVTF FPR -> FPR is 4 cyclces.
4630 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4631 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
/external/clang/lib/CodeGen/
DTargetInfo.cpp3162 llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr"); in EmitVAArg() local
3168 llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR, in EmitVAArg()
3171 llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR, in EmitVAArg()
3194 FPR = Builder.CreateAdd(FPR, Builder.getInt8(1)); in EmitVAArg()
3195 Builder.CreateStore(FPR, FPRPtr); in EmitVAArg()

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